Senior Principal Application Engineer — Digital Implementation & Signoff (RTL2 GDS)
Cadence Design SystemsJob Title
Senior Principal Application Engineer — Digital Implementation & Signoff (RTL2 GDS)
Role Summary
Senior technical field application engineer working with customers on digital implementation, place-and-route, and signoff flows to meet power, performance, and area (PPA) goals and accelerate design closure.
Work directly with customers and Cadence R&D to drive tool adoption, influence product direction, and improve design methodologies for advanced-node semiconductor designs.
Experience Level
Senior — requires 10+ years of industry physical design experience (physical/backend digital design and signoff).
Responsibilities
Primary responsibilities include customer engagement, technical enablement, and collaboration with product teams.
- Provide technical support and consulting to customers on backend digital design implementation and signoff (place & route, timing/power closure, IR drop).
- Guide customers on using Cadence technologies to achieve design goals and schedules.
- Conduct technical presentations, demos, evaluations, and benchmarks.
- Collaborate with R&D to capture customer requirements and influence tool and methodology enhancements.
- Drive adoption and proliferation of tools and flows across customer projects.
- Develop and adapt flows and automation using Tcl, Python, or similar scripting to improve results.
- Capture and disseminate best practices and lessons learned from engagements.
Requirements
Required technical skills and experience.
- 10+ years of industry physical design experience.
- Strong knowledge of digital design fundamentals, semiconductor concepts, and static timing analysis.
- Experience with IC digital implementation flows and backend EDA tools (place & route, IR drop analysis, timing and power closure).
- Experience at advanced nodes (10 nm and below).
- Proficiency in scripting languages such as Tcl, Perl, or Python.
- Strong customer-facing communication, problem-solving, and collaboration skills.
- Self-driven with a focus on continuous learning and technical leadership.
- Nice-to-have: experience with front-end EDA tools (synthesis, DFT, LEC) and familiarity with Cadence products such as Genus, Innovus, Tempus, Voltus, Modus, Conformal, ICC/ICC2, DC, or PrimeTime.
- Nice-to-have: experience with advanced nodes 5 nm and below.
Education Requirements
Minimum: BS in Computer Science, Computer Engineering, Electrical Engineering, or a related field. Preferred: MS in a related technical discipline. (Degrees mentioned in the source; equivalent practical experience may be considered per company policy.)
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
