Senior Pre-Silicon Verification Engineer

Job Title

Senior Pre-Silicon Verification Engineer

Role Summary

Senior engineer responsible for pre-silicon verification of mixed-signal and digital IP to validate functional, performance, power and PVT behavior before fabrication. The role develops verification strategies, behavioral models, and scalable verification environments that support regression and system-level verification.

Work closely with analog and digital architects, RTL developers, and physical design teams to ensure pre-silicon results meet design specifications and correlate to post-silicon behavior.

Experience Level

Senior-level — typically requires 5+ years in digital or mixed-signal verification and 3+ years in pre-silicon verification environment architecture.

Responsibilities

Primary responsibilities include verification, modeling, simulation, and cross-functional debugging.

• Perform functional verification of digital and mixed-signal logic, including analog behavioral modeling, AMS simulation, and real number modeling.
• Create verification environments that model analog-digital interactions and validate designs across PVT corners.
• Develop IP verification plans, testbenches, and scalable frameworks supporting regression and CI for digital and analog flows.
• Execute verification plans; analyze power, timing and performance metrics; run system-level simulations and corner-case analysis.
• Replicate, root cause and debug complex pre-silicon issues and implement corrective actions.
• Collaborate with architects, RTL and physical design teams; document test plans and drive technical reviews and process improvements.

Requirements

Summary of must-have and nice-to-have skills and experience.

Must-have:

• 5+ years of experience in digital design verification or mixed-signal verification.
• 3+ years experience developing pre-silicon verification environment architecture.
• Experience with mixed-signal IP or system-level verification and with digital verification methodologies (UVM/SystemVerilog).
• Scripting experience (Python preferred; Perl, HTML or similar acceptable).

Nice-to-have:

• Experience with SerDes, PLLs or SerDes PHY verification.
• Experience with mixed-signal verification methodology (MSV), gate-level simulation (GLS), DFT, ATE, HVM.
• Experience driving verification methodology changes and initiatives.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering or a STEM field is required. A Master’s degree in Electrical Engineering, Computer Engineering or a related technical field is preferred. Equivalent practical experience (combination of industry experience, internships, or relevant coursework/research) is acceptable.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.