Senior Power Integrity Engineer - LPU Packaging

Job Title

Senior Power Integrity Engineer - LPU Packaging

Role Summary

Senior Power Integrity (PI) engineer on the LPU Packaging team responsible for defining and validating power-delivery networks (chip → package → board → system) for high-performance GPU products. You will set PI specifications, develop extraction and simulation flows, and lead lab validation and debug during hardware bring-up.

Experience Level

Senior — requires substantial experience; the posting requests 10+ years of relevant power integrity experience.

Responsibilities

Work across chip, package, board, and system teams to architect and validate PDNs for high-power accelerator products.

• Define PDN targets (impedance, droop, noise, transient response) and own PI specifications and methodology for assigned products.
• Architect package-level PDNs and collaborate on bump/ball maps, vias, and decoupling strategies for FCBGA and advanced 25D/3D integrations.
• Drive board- and system-level PI design including stack-up, plane partitioning, decap placement, and VRM interfaces.
• Perform PI extraction and simulation; develop integrated chip–package–board co-simulation flows using industry tools.
• Generate reusable PI models (SPICE, S-parameters, IBIS-AMI) for internal and external use.
• Plan and execute lab validation to correlate measured impedance, noise, and droop against simulations and specs.
• Debug system-level issues such as rail noise, jitter-induced errors, resets, and margin loss during hardware testing.

Requirements

Must-have technical skills, tools, and domain experience. Nice-to-have items listed separately.

• 10+ years of relevant power integrity experience for high-current, low-voltage rails in GPUs, ASICs, or CPUs.
• Proven ownership of chip–package–board PDN design and sign-off process.
• Hands-on experience with high-power, high-pin-count packages (FCBGA, 25D/3D, HBM integrations).
• Experience co-designing bump/ball maps, power/ground planes, and decoupling capacitor networks.
• Proficiency with frequency-domain impedance analysis and time-domain transient/droop simulation tools (examples: PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, SPICE).
• Strong understanding of board-level PDN design: stack-up definition, plane partitioning, VRM placement on high-layer-count accelerator boards.
• Hands-on lab experience using VNAs, oscilloscopes, and PDN analyzers for PI validation.

Nice-to-have:

• Leadership of end-to-end PI for a major GPU, CPU, or ASIC program through mass production.
• Experience with data center/cloud hardware and rack-level power distribution considerations.
• Background in co-design of SI and PI for high-speed interfaces (PCIe, NVLink, CXL, Ethernet SerDes).
• Clear communication skills for presenting PDN trade-offs and risks to technical and program stakeholders.

Education Requirements

MS or PhD in Electrical Engineering or a related field, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.