Senior Power Integrity Engineer - LPU Packaging

Job Title

Senior Power Integrity Engineer - LPU Packaging

Role Summary

Join the LPU Packaging team to define and validate power-delivery networks (PDNs) across chip, package, and board for high-performance GPUs and advanced package integrations.

This role leads PI specification, simulation, and lab validation to ensure PDN targets for impedance, droop, noise, and transient response are met for products from design through production.

Experience Level

Senior-level. Requires 12+ years of relevant work experience in Power Integrity.

Responsibilities

Accountable for PDN architecture, simulation, validation, and cross-team co-optimization.

• Define PDN targets and PI methodology for assigned products, including GPU, HBM, and SerDes rails.
• Architect package-level PDNs and advise on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations.
• Drive board- and system-level PI planning: decap placement, VRM interfaces, and rack-level considerations while coordinating with SI, thermal, and mechanical teams.
• Perform PI extraction and simulation and develop chip–package–board co-simulation flows.
• Generate reusable PI models (SPICE, S-parameter, IBIS-AMI) for internal and external use.
• Define and execute lab validation plans; correlate measured impedance, noise, and droop against simulations and specs.
• Debug complex system-level issues such as rail noise, jitter-induced errors, resets, and margin loss during hardware testing.

Requirements

Must-have technical skills and experience.

• 12+ years of hands-on Power Integrity experience for high-current, low-voltage rails in large GPUs, ASICs, or CPUs.
• Proven ownership of chip-package-board PDN design and sign-off processes.
• Experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packages.
• Direct experience co-designing bump/ball maps, power/ground planes, and decoupling capacitor networks.
• Proficiency in frequency-domain PDN impedance analysis and time-domain transient/droop simulation tools (examples: PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, SPICE).
• Deep understanding of board-level PDN design: stack-up, plane partitioning, and VRM placement on high-layer-count accelerator boards.
• Experience executing lab measurements using VNAs, oscilloscopes, and PDN analyzers to validate PI specifications.

Nice-to-have:

• Leadership of end-to-end PI for a major GPU/CPU/ASIC program through mass production.
• Experience with data-center or cloud hardware and rack-level power distribution.
• Background in co-designing SI and PI for high-speed interfaces (PCIe, NVLink, CXL, Ethernet SerDes) to mitigate jitter/noise coupling.
• Strong communication skills for explaining PI trade-offs to technical teams and stakeholders.

Education Requirements

MS or PhD in Electrical Engineering or a related field, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.