Senior Power Integrity Co-Design Engineer

Job Title

Senior Power Integrity Co-Design Engineer

Role Summary

Senior engineer on the SCG Architecture team responsible for architecting and delivering voltage-noise (di/dt) mitigation across silicon, package, board, and platform. The role translates product noise targets into shipped specifications and feeds silicon findings into next-generation designs.

Experience Level

Senior — typically requires 5+ years of experience in silicon power integrity, voltage noise, or PDN.

Responsibilities

Owner for system-level noise mitigation and the co-design trade-offs across silicon, package, board, and platform.

• Architect voltage-noise mitigation across the full stack and make co-design trade-offs between silicon, package, board, and platform.
• Collaborate with Speed, Power, Reliability, Circuit Design, Power-Arch, ASIC, and platform teams to define and close product-level voltage noise targets.
• Build and own Sim-to-Si correlation methodology for noise and lead characterization efforts.
• Model and prototype noise-mitigation features (transient sensing, droop response, mitigation IP) and codify them for future programs.
• Lead resolution of critical noise issues during bring-up and ensure documented sign-off at shipment.
• Drive architecture-level tradeoffs across voltage/frequency, power, noise, reliability, and thermal considerations.

Requirements

Must-have technical skills, hands-on experience, and collaboration capabilities.

• 5+ years in silicon power integrity, voltage noise, or PDN.
• Deep expertise in at least one area: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decoupling budget, or voltage regulator response.
• Hands-on silicon experience: bring-up, characterization, and correlation; comfortable using scopes, probes, DAQ, and simulators.
• Strong Sim-to-Si correlation instincts and the ability to identify model vs silicon discrepancies.
• System-level judgment to make product-focused decisions across multiple component teams.
• Proven ability to drive multi-functional decisions in a matrixed environment and deliver documented sign-offs.

Nice-to-have:

• Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation.
• Experience with GPU, CPU, or AI-accelerator silicon families or hyperscaler-class designs.
• Experience applying ML/AI to noise modeling, transient prediction, or feature optimization.
• Track record of codifying methodology into reusable workflows or tooling.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.