Senior PnR (Place and Route) Engineer

Job Title

Senior PnR (Place and Route) Engineer

Role Summary

Drive digital backend (physical) implementation for SoC/IP designs from RTL to GDSII. Work closely with RTL designers to define partitioning and physical architecture and to ensure timing, power and area goals are met for tapeout in advanced nodes.

Experience Level

Senior — minimum of 5 years of hands-on place-and-route / physical design experience, including working with 16nm FinFET and smaller process nodes.

Responsibilities

Primary responsibilities include implementing and delivering physical design for large SoC/IP blocks and supporting signoff flows.

• Floorplanning, placement, clock tree synthesis (CTS), and routing.
• Timing closure, clock and power distribution planning and optimization.
• Perform physical verification steps: DRC/LVS, antenna checks, and generation of GDSII and .lib files.
• IR drop analysis, SPEF generation, and reliability checks including EM and signal integrity (crosstalk) analysis.
• Execute full RTL-to-GDSII flow and drive physical aspects early in the design cycle.
• Identify physical design and flow issues, propose solutions, and drive execution to meet schedule and die-size constraints.
• Collaborate with RTL, verification and tapeout teams to ensure successful silicon bring-up.

Requirements

Must-have technical skills and experience; concise list of baseline requirements followed by a few preferred items.

• Proven physical design experience with recent successful tapeouts in deep-submicron and FinFET technologies.
• Expertise in partition-level P&R implementation including floorplanning, clock & power distribution, and timing closure.
• Experience with PD construction and analysis flows and methodology; familiarity with signoff-quality flows.
• Hands-on experience with industry-standard P&R tools (Cadence PnR toolset preferred) and understanding of their algorithms and limitations.
• Experience with large SoC/IP designs and high-frequency designs (frequencies >500 MHz).
• Practical experience on 16nm FinFET and lower nodes.
• Strong scripting skills in Tcl and Python.
• Strong communication skills and ability to deliver to tight schedules and die-size targets.
• Nice-to-have: exposure to low-power techniques and good understanding of Verilog/VHDL.

Education Requirements

B.E. / B.Tech. or M.E. / M.Tech. in VLSI (or closely related electrical/semiconductor engineering degrees) were specified in the source posting.

About the Company

Company: Omni Design Technologies

Headquarters: Hyderabad, India

Omni Design Technologies specializes in the development of advanced solutions for electronic design automation, focusing on ASIC and FPGA verification processes. The company provides high-quality verification tools and resources for engineers in the semiconductor industry, ensuring efficient design and reliable performance.