Senior Physical Design Engineer - Static Timing Analysis

Job Title

Senior Physical Design Engineer - Static Timing Analysis

Role Summary

Senior STA engineer on the Cloud-Scale Machine Learning Acceleration team responsible for block- and full-chip static timing analysis and timing closure for AWS cloud server platforms (including products such as AWS Inferentia).

The role focuses on developing and maintaining STA flows, debugging timing issues, automating timing runs and reports, and collaborating with physical design, RTL and architecture teams to meet performance, quality and cost targets.

Experience Level

Senior — hiring guidance: BS + 8 years, MS + 6 years, or PhD + 4 years in relevant fields (see Education Requirements).

Responsibilities

Key responsibilities include STA flow development, timing constraint work, and cross-team collaboration.

• Develop and maintain block and full-chip static timing analysis flows.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run static timing analysis, interpret results, and provide actionable feedback.
• Recommend and produce ECOs and constraint fixes to resolve timing issues.
• Develop scripts to automate timing runs and generate standardized reports.
• Collaborate closely with physical design, RTL, and architecture teams to achieve timing closure.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Proficiency in scripting (Perl, Python, or JavaScript).
• Expertise in timing analysis fundamentals and STA methodologies.
• 3+ years' hands-on experience performing Static Timing Analysis.
• 3+ years' experience developing timing constraints.
• Experience with STA EDA tools (examples: PrimeTime, Tempus, or equivalent).
• Understanding of ASIC physical design flow from RTL-to-GDSII.
• Familiarity with sign-off activities such as IR/EM, physical verification, and DFT.

Nice-to-have:

• Experience mentoring or leading engineering workstreams.
• Expertise developing STA and ECO flows (e.g., PT-DMSA, Tempus-ECO, Tweaker).
• Experience at advanced nodes (16 nm or below).
• Knowledge of parasitic extraction tools (STAR-RC, Quantus) and circuit-level analysis (SPICE/SPECTRE).
• Experience with timing of IO interfaces (DDR, HBM, PCIe, die-to-die).

Education Requirements

BS + 8 years, MS + 6 years, or PhD + 4 years in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field.

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.