Senior Physical Design Engineer — Static Timing Analysis, Cloud-Scale Machine Learning (Annapurna Labs)

Job Title

Senior Physical Design Engineer — Static Timing Analysis, Cloud-Scale Machine Learning (Annapurna Labs)

Role Summary

The Senior Physical Design STA Engineer will develop and maintain static timing analysis flows and constraints for block- and full-chip designs used in cloud-scale machine-learning hardware platforms. You will work on optimization, timing closure, and cross-functional collaboration with RTL, architecture, and physical-design teams.

This role sits on the Cloud-Scale Machine Learning Acceleration team and contributes to hardware used in AWS data centers, including machine-learning inference products.

Experience Level

Senior. Candidates should have substantial experience in static timing analysis and ASIC physical design; the posting specifies at least 3+ years of hands-on STA experience and additional senior-level experience expectations in other qualifications.

Responsibilities

Primary responsibilities include creating and operating STA flows, diagnosing timing issues, and collaborating across teams to achieve timing closure.

• Develop and maintain block- and full-chip static timing analysis (STA) flows.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run STA, analyze results, and provide actionable feedback to designers and leads.
• Recommend and implement fixes for timing issues (generate ECOs, correct constraints).
• Automate timing analysis runs and report generation through scripting and tools.
• Collaborate closely with physical design, RTL, and architecture teams to meet performance, quality, and cost targets.

Requirements

Must-have technical skills and experience.

• Hands-on experience with STA tools (examples: Synopsys PrimeTime, Siemens/Ansys Tempus, or equivalent).
• Proven knowledge of timing analysis fundamentals and timing-constraint development (minimum 3+ years STA and 3+ years constraint work).
• Scripting proficiency (Perl, Python, or JavaScript) to automate flows and reports.
• Understanding of ASIC physical-design flow from RTL-to-GDSII and familiarity with sign-off activities (IR/EM, physical verification, DFT).

Nice-to-have / preferred:

• Experience mentoring, leading, or coaching engineers.
• Expertise building STA flows and ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker).
• Experience with advanced process nodes (16nm and below) and parasitic extraction tools (STAR-RC, Cadence Quantus, or equivalent).
• Circuit-level analysis experience with SPICE/Spectre and timing experience on high-speed IOs (DDR, HBM, PCIe, die-to-die interfaces).

Education Requirements

Degree and experience combinations specified: BS plus 8 years, MS plus 6 years, or PhD plus 4 years of professional experience in Electrical Engineering (EE) or Computer Science (CS).

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.