Senior Physical Design Engineer - Static Timing Analysis (Annapurna Labs, Cloud-Scale ML)

Job Title

Senior Physical Design Engineer - Static Timing Analysis (Annapurna Labs, Cloud-Scale Machine Learning)

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team to design and optimize hardware for AWS data-center platforms (for example, AWS Inferentia). The role focuses on static timing analysis (STA) and timing closure for block- and full-chip physical design flows.

This is a hands-on engineering role that requires collaboration with physical design, RTL, and architecture teams to deliver high-performance, production-quality silicon at scale.

Experience Level

Senior-level. Experience expectation: typically 8+ years of relevant industry experience (see Education Requirements for degree-to-experience mapping).

Responsibilities

Primary responsibilities include developing STA flows, performing timing analysis, and guiding fixes to achieve timing closure.

• Develop and maintain block- and full-chip static timing analysis flows and automation scripts.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run STA, analyze results, and provide actionable feedback to design teams and leads.
• Recommend and implement ECOs and constraint fixes to resolve timing issues.
• Generate timing reports and automate reporting and regression flows.
• Collaborate closely with RTL/architecture and other physical-design engineers to meet performance, quality, and schedule targets.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Proficiency in scripting languages such as Perl, Python, or JavaScript.
• Strong understanding of timing analysis fundamentals and timing constraint development.
• At least 3+ years performing Static Timing Analysis and 3+ years developing timing constraints.
• Experience with STA EDA tools (examples: PrimeTime, Tempus, or equivalent).
• Practical knowledge of ASIC physical design flow from RTL-to-GDSII.
• Familiarity with sign-off activities such as IR/EM analysis, physical verification, and DFT.

Preferred / nice-to-have:

• Experience mentoring, leading, or coaching engineering teams.
• Expertise developing STA flows and ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker).
• Experience with advanced process nodes (16nm and below).
• Familiarity with parasitic extraction tools (examples: STAR-RC, Quantus) and circuit-level analysis tools (SPICE/SPECTRE).
• Experience with timing of I/O interfaces such as DDR, HBM, PCIe, and die-to-die interfaces.

Education Requirements

BS + 8 years, MS + 6 years, or PhD + 4 years in Electrical Engineering or Computer Science (as specified in the posting).

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.