Senior Physical Design Engineer — Static Timing Analysis (Annapurna Labs, Cloud-Scale Machine Learning)

Job Title

Senior Physical Design Engineer — Static Timing Analysis (Annapurna Labs, Cloud-Scale Machine Learning)

Role Summary

Work on physical design and static timing analysis (STA) for cloud-scale ML acceleration hardware. The role focuses on developing and maintaining STA flows, writing and validating timing constraints, running sign-off timing analysis, and guiding ECO/fix efforts across block and full-chip designs.

This position sits on the Cloud-Scale Machine Learning Acceleration team and collaborates with physical design, RTL, and architecture teams to optimize performance, quality, and cost of server-class ASICs.

Experience Level

Senior — experienced engineer with leadership in STA and physical design; expect multiple years of relevant ASIC/STA experience.

Responsibilities

Primary technical responsibilities and team interactions.

• Develop and maintain block- and full-chip STA flows and automation scripts.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run Static Timing Analysis using sign-off tools and produce actionable reports.
• Diagnose timing failures and recommend/implement fixes (generate ECOs, update constraints).
• Automate timing runs and reporting to accelerate delivery and feedback loops.
• Collaborate closely with physical design, RTL, and architecture teams to close timing and meet project goals.
• Provide technical leadership in applying new technologies to large-scale deployments.

Requirements

Core technical skills and preferred skills for the role. Degrees are summarized in the Education Requirements section below.

Must-have:

• Hands-on experience with Static Timing Analysis (STA) and timing constraint development (multi-year experience expected).
• Experience with STA/sign-off tools (examples: Synopsys PrimeTime, Siemens/Calibre/Tempo/Apache tools, Mentor Tempus, or similar).
• Proficiency in scripting for automation (Perl, Python, or JavaScript).
• Practical understanding of ASIC physical design flow from RTL-to-GDSII.
• Familiarity with sign-off activities such as IR/EM analysis, physical verification, and DFT.
• Ability to debug timing issues and drive ECO-based fixes.

Nice-to-have:

• Experience developing and mentoring others; leading technical efforts.
• Experience with ECO flows and ECO tools (examples: PT-DMSA, Tempus-ECO, Tweaker).
• Experience at advanced process nodes (16nm and below) and parasitic extraction tools (STAR-RC, Cadence Quantus, etc.).
• Circuit-level analysis experience (SPICE, Spectre) and timing of high-speed I/O interfaces such as DDR, HBM, PCIe, die-to-die links.

Education Requirements

Bachelor's degree (BS) plus 8+ years, Master's degree (MS) plus 6+ years, or PhD plus 4+ years in Electrical Engineering, Computer Science, or a related technical field (as specified in the posting).

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.