Senior Physical Design Engineer - Static Timing Analysis

Job Title

Senior Physical Design Engineer - Static Timing Analysis

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team to design and optimize hardware used in AWS data centers, focusing on static timing analysis (STA) for high-performance cloud server platforms.

This role leads STA flow development, timing constraint creation, and cross-functional timing closure efforts across block and full-chip designs.

Experience Level

Senior-level. Typical experience is 8+ years overall, with at least 3+ years performing Static Timing Analysis.

Responsibilities

The role executes and improves STA on blocks and full-chip designs and provides actionable guidance to design teams.

• Develop and maintain block- and full-chip STA flows.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run STA, analyze results, and communicate findings to RTL, architecture, and physical design teams.
• Recommend and implement fixes for timing issues (generate ECOs, correct constraints).
• Develop scripts to automate timing runs and generate reports.
• Collaborate closely with physical design, RTL/architecture, and verification teams to achieve timing closure.

Requirements

Must-have technical skills and experience required to perform the core responsibilities.

• Proven experience with Static Timing Analysis (3+ years).
• Experience developing timing constraints and timing analysis fundamentals.
• Familiarity with STA EDA tools such as PrimeTime or Tempus.
• Experience scripting in Perl, Python, or JavaScript to automate flows and reports.
• Understanding of ASIC physical design flow from RTL to GDSII.
• Knowledge of other sign-off activities: IR/EM, physical verification, and DFT.

Nice-to-have

• Experience mentoring, leading, or coaching engineering teams.
• Experience developing STA flows and ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker).
• Experience in advanced nodes (16nm or below) and parasitic extraction tools (STAR-RC, Quantus).
• Circuit-level analysis experience with SPICE/SPECTRE and timing of IO interfaces (DDR, HBM, PCIe, Die-to-Die).

Education Requirements

Required: Bachelor's, Master's, or PhD in Electrical Engineering or Computer Science. The posting specifies degree-to-experience mappings: BS + 8 years, MS + 6 years, or PhD + 4 years. (If non-degree equivalent experience is available, it should meet the experience expectations in the role.)

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.