Senior Physical Design Engineer — Static Timing Analysis

Job Title

Senior Physical Design Engineer — Static Timing Analysis

Role Summary

Responsible for block- and full-chip static timing analysis (STA) for cloud-scale ML accelerator platforms. Work on timing constraint development, timing sign-off flows, ECO guidance, and automation to support ASIC physical design delivery.

Member of the Cloud-Scale Machine Learning Acceleration team focused on improving performance, quality, and cost of AWS hardware deployments.

Experience Level

Senior level. Posting indicates advanced experience expectations (refer to Education Requirements for degree and years guidance) and at least 3+ years of hands-on STA experience.

Responsibilities

Core responsibilities include design, validation, and automation of STA flows and providing timing closure guidance.

• Develop and maintain block- and full-chip static timing analysis flows.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run STA, analyze results, and provide actionable feedback to designers and architects.
• Recommend and implement timing fixes (generate ECOs, constraint fixes).
• Develop scripts and automation to run timing analysis and generate reports.
• Collaborate closely with physical design, RTL, and architecture teams.

Requirements

Must-have technical skills and tools experience; preferred items listed separately.

• Must-have: 3+ years performing Static Timing Analysis; strong fundamentals in timing analysis and timing constraint development.
• Experience with STA EDA tools (examples: PrimeTime, Tempus, or equivalent).
• Familiarity with ASIC physical design flow from RTL-to-GDSII and sign-off activities (IR/EM, physical verification, DFT).
• Proficiency in scripting for automation (Perl, Python, or JavaScript).
• Ability to debug timing issues, generate ECOs, and guide implementation teams.
• Nice-to-have: mentoring or technical leadership experience; expertise in STA flow development and ECO flows (PT-DMSA, Tempus-ECO, Tweaker); experience with advanced nodes (16nm and below); parasitic extraction tools (STAR-RC, Quantus); circuit-level analysis (SPICE/SPECTRE); timing of IO interfaces (DDR, HBM, PCIe, Die-to-Die).

Education Requirements

Degree and experience guidelines: BS + 8 years, MS + 6 years, or PhD + 4 years in Electrical Engineering or Computer Science. (These degree+experience combinations are stated in the posting.)

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.