Senior Physical Design Engineer — Static Timing Analysis

Job Title

Senior Physical Design Engineer — Static Timing Analysis

Role Summary

Senior STA engineer on the Cloud-Scale Machine Learning Acceleration team responsible for block- and full-chip static timing analysis, timing-closure guidance, and automation for AWS data center hardware platforms (including Inferentia-class designs).

You will develop and maintain STA flows, write and validate timing constraints, run sign-off analyses, and collaborate with physical design, RTL and architecture teams to improve performance, quality, and cost.

Experience Level

Senior. The posting specifies senior-level qualifications; typical experience guidance is on the order of multiple years in STA and physical design (see Education Requirements for degree + experience combinations).

Responsibilities

Core responsibilities include:

• Develop and maintain block- and full-chip static timing analysis (STA) flows and automation scripts.
• Write, debug and validate timing constraints for blocks and full-chip designs.
• Run STA, analyze results, and provide frequent feedback to design teams and leads.
• Recommend and implement fixes for timing issues (generate ECOs, correct constraints).
• Generate timing reports and dashboards to track closure progress.
• Collaborate with physical design, RTL/architecture, and verification teams to resolve timing and sign-off issues.

Requirements

Must-have technical skills and experience:

• Strong expertise in timing analysis fundamentals and STA methodologies.
• 3+ years hands-on Static Timing Analysis experience using commercial EDA tools (examples: PrimeTime, Tempus, or similar).
• 3+ years experience developing timing constraints and constraint verification.
• Proficiency with scripting for automation (Perl, Python, or JavaScript).
• Solid understanding of ASIC physical design flow from RTL to GDSII and related sign-off activities (IR/EM, physical verification, DFT).

Nice-to-have / preferred:

• Experience mentoring or leading engineers.
• Experience developing STA/ECO flows and using ECO tools (examples: PT-DMSA, Tempus-ECO, Tweaker).
• Experience on advanced process nodes (16nm and below).
• Familiarity with parasitic extraction tools (STAR-RC, Quantus) and circuit-level analysis (SPICE, SPECTRE).
• Experience with timing of high-speed IO interfaces (DDR, HBM, PCIe, Die-to-Die).

Education Requirements

Degree + experience combinations listed in the posting: BS + 8 years, MS + 6 years, or PhD + 4 years in Electrical Engineering or Computer Science (or equivalent experience).

About the Company

Company: Amazon

Headquarters: Seattle, Washington, United States

Amazon is a global leader in e-commerce and cloud computing, committed to delivering fast, reliable services across diverse sectors. The company's innovative technologies include AWS, Kindle, and Echo, as well as developing low Earth orbit satellite networks for improved internet connectivity worldwide.