Senior Physical Design Engineer - Static Timing Analysis

Job Title

Senior Physical Design Engineer - Static Timing Analysis

Role Summary

Senior Physical Design STA engineer on the Cloud-Scale Machine Learning Acceleration team responsible for static timing analysis, constraint development, and timing closure for server-class ASICs (for example, AWS Inferentia).

The role involves developing and maintaining STA flows for block- and full-chip analysis, advising RTL and physical-design teams on timing fixes, and automating timing runs and reports.

Experience Level

Senior-level. Candidates should have hands-on STA experience (see Requirements) and demonstrated ability to lead technical work and mentor others.

Responsibilities

Primary responsibilities include running and improving STA flows, diagnosing timing problems, and collaborating across teams.

• Develop and maintain block- and full-chip static timing analysis flows.
• Write, debug, and validate timing constraints for blocks and full-chip designs.
• Run STA, analyze results, and provide actionable feedback to engineers and leads.
• Recommend and implement timing fixes (generate ECOs, correct constraint issues).
• Develop scripts to automate STA runs and generate timing reports.
• Collaborate closely with physical design, RTL, and architecture teams.

Requirements

Must-have technical skills and experience; preferred items are listed separately.

• Must-have: Proficiency in scripting (Perl, Python, or JavaScript).
• Expertise in timing-analysis fundamentals and signoff methodology.
• 3+ years performing Static Timing Analysis and 3+ years developing timing constraints.
• Experience with STA EDA tools (examples: PrimeTime, Tempus, or equivalents).
• Understanding of ASIC physical design flow from RTL to GDSII and sign-off activities (IR/EM, physical verification, DFT).
• Nice-to-have: Experience mentoring or leading engineers; developing STA flows and ECO flows (PT-DMSA, Tempus-ECO, Tweaker); advanced-node experience (16nm or below); parasitic extraction tools (STAR-RC, Quantus); circuit-level analysis (SPICE/SPECTRE); timing of high-speed IO (DDR, HBM, PCIe, Die-to-Die).

Education Requirements

Qualification combinations specified: BS + 8 years, MS + 6 years, or PhD + 4 years in Electrical Engineering, Computer Science, or a related technical field.

Amazon is an equal opportunity employer. Candidates requiring reasonable accommodation during the application or hiring process may request assistance.

About the Company

Company: Amazon

Headquarters: Seattle, Washington, United States

Amazon is a global leader in e-commerce and cloud computing, committed to delivering fast, reliable services across diverse sectors. The company's innovative technologies include AWS, Kindle, and Echo, as well as developing low Earth orbit satellite networks for improved internet connectivity worldwide.