Senior Physical Design Engineer - Static Timing Analysis

Job Title

Senior Physical Design Engineer - Static Timing Analysis

Role Summary

Senior STA engineer on the Cloud‑Scale Machine Learning Acceleration team responsible for developing and maintaining block- and full‑chip static timing analysis flows, timing constraints, automation, and guidance to resolve timing issues. Work closely with physical design, RTL, and architecture teams to deliver production cloud server platforms.

Experience Level

Senior-level. The posting specifies degree-plus-experience benchmarks (BS + 8 years, MS + 6 years, PhD + 4 years) and expects hands-on STA experience and timing-constraint development.

Responsibilities

Primary responsibilities include STA flow development, timing analysis, and cross‑team collaboration:

• Develop and maintain block- and full‑chip static timing analysis flows.
• Author, debug, and validate timing constraints for blocks and full chip.
• Run STA tools, analyze results, and provide actionable feedback to design teams.
• Recommend and implement timing fixes (ECOs) and resolve constraint issues.
• Develop scripts to automate STA runs and generate timing reports.
• Collaborate with physical design, RTL, and architecture teams to meet performance, quality, and cost targets.

Requirements

Must-have skills and experience:

• 3+ years performing Static Timing Analysis using industry EDA tools (examples: PrimeTime, Tempus).
• 3+ years developing timing constraints for complex ASIC designs.
• Strong knowledge of timing analysis fundamentals and interpretation of STA reports.
• Experience with ASIC physical design flow from RTL-to-GDSII and sign‑off activities (IR/EM, physical verification, DFT).
• Proficiency in scripting (Perl, Python, or JavaScript) for automation and reporting.

Nice-to-have:

• Experience developing STA and ECO flows (examples: PT‑DMSA, Tempus‑ECO, Tweaker).
• Experience at advanced process nodes (16nm or below) and with parasitic extraction tools (STAR‑RC, Quantus).
• Circuit‑level analysis experience (SPICE/SPECTRE) and timing of high‑speed IO interfaces (DDR, HBM, PCIe, die‑to‑die).
• Experience mentoring or leading engineering teams.

Education Requirements

BS, MS, or PhD in Electrical Engineering or Computer Science. The posting specifies BS + 8 years, MS + 6 years, or PhD + 4 years of relevant experience.

About the Company

Company: Amazon Web Services

Headquarters: Seattle, Washington, USA

Amazon Web Services (AWS) provides a comprehensive and evolving cloud computing platform that includes infrastructure as a service (IaaS), platform as a service (PaaS), and software as a service (SaaS). AWS allows business and developers to use a wide range of cloud services for computing power, storage, and content delivery, among others, thus fostering innovation and enabling faster deployment of applications. AWS is designed to be scalable, flexible, and cost-effective across industries worldwide.