Senior Physical Design Engineer / Lead

Job Title

Senior Physical Design Engineer / Lead

Role Summary

Lead backend physical implementation for FPGA/SoC devices from RTL/netlist to GDSII, focusing on floorplanning, placement, CTS, routing, sign-off, and manufacturability. Work across architecture, RTL, CAD/EDA, DFT, manufacturing and packaging teams to meet performance, power, area, and yield targets.

Experience Level

Senior — requires extensive industry experience (10+ years of physical design or SoC/backend implementation experience).

Responsibilities

Deliver and improve physical implementation flows, take ownership of block and full-chip implementation tasks, and mentor junior engineers.

• Lead and execute floorplanning, power planning, placement, clock tree synthesis (CTS), routing, ECOs, extraction and sign-off preparation from netlist to GDSII.
• Optimize performance, timing closure, power reduction and area across blocks and full-chip hierarchies.
• Collaborate with front-end design, architecture, CAD/EDA tool teams to define and meet timing, power, and DFT requirements.
• Develop and maintain automation, flows and scripts (Tcl, Python, Perl) to improve QoR and turnaround time.
• Perform timing, power, EM/IR, signal/noise, DRC/LVS/ERC verification and prepare for sign-off.
• Integrate FPGA-specific implementation aspects (fabric routing, configurable logic placement, I/O ring, on-chip power domains).
• Coordinate with manufacturing and packaging partners to ensure manufacturability, reliability and yield for high-volume production.
• Debug implementation issues and work with CAD tool vendors and internal tool teams to resolve tool limitations.
• Mentor junior engineers and document flows and best practices.

Requirements

Minimum technical experience and skills required for the role.

• 10+ years hands-on experience in digital ASIC and/or SoC physical design including synthesis, floorplanning, place-and-route, CTS, routing, ECOs and sign-off.
• Extensive experience with industry EDA implementation and signoff tools (examples: Synopsys IC Compiler II/Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Mentor Calibre) — ~8+ years.
• 5+ years scripting and automation experience in Tcl; experience with Python/Perl/Shell for flow automation.
• 8+ years applying physical design methodologies: floorplanning, power planning, placement, CTS, routing and timing closure.
• 5+ years implementing low-power methodologies: clock gating, multi-power domain implementation and power-aware physical design.
• 5+ years performing static timing analysis and timing closure for high-speed designs; experience with power integrity (IR drop), EM, and signal integrity analyses.
• Experience with physical verification and signoff activities (DRC, LVS, ERC, DFM) and manufacturing verification flows.
• Experience with chip integration tasks: block integration, pin assignment, timing/constraint push-down, hierarchical implementation.
• Experience with bump planning, RDL routing, MiM capacitor planning, ESD signoff or package-aware physical implementation.
• Ability to collaborate across RTL, architecture, CAD/EDA, manufacturing, packaging and DFT teams throughout implementation lifecycle.
• U.S. export authorization eligibility as required for applicants.

• Experience with advanced process nodes (7nm, 5nm or below) and high-frequency designs (>=1 GHz).
• Direct experience with FPGA or programmable logic physical implementation flows and FPGA architecture knowledge.
• Experience in high-volume manufacturing, yield/DFM/DFY optimization, and AI/ML-assisted physical design tools (e.g. Synopsys DSO.ai, Cadence Cerebrus).
• Prior experience mentoring teams or leading physical implementation efforts.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline is required. A Master's degree in Electrical Engineering, Computer Engineering, or a related field is preferred. The role also expects ~10+ years of industry physical design/SoC backend experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.