Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

Join Microsoft’s Compute Silicon & Manufacturing Engineering (CSME) within Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) to deliver physical-design solutions for datacenter SoCs including power analysis and optimization. The role is an individual contributor position focused on physical implementation, signoff, and methodology for large SOC blocks.

Experience Level

Senior. Preferred 7+ years in semiconductor design; role requires multiple years of hands-on physical design and signoff experience (see Requirements for specifics).

Responsibilities

Deliver end-to-end physical implementation and signoff while collaborating with cross-functional teams to meet power, performance, area, quality, and schedule goals.

• Own SOC low-power design methodology and power signoff for assigned blocks.
• Drive PPA optimization and methodology exploration across RTL, synthesis, floorplan, place-and-route, and signoff.
• Execute RTL-to-GDS implementation for medium to large SOC partitions.
• Lead synthesis, floorplanning, placement, routing, extraction, timing closure, and physical verification activities.
• Ensure completion of all signoff stages: timing, physical verification, EMIR, formal equivalence, and low-power verification.
• Coordinate with CAD/PD flow, RTL/design/DFT, architecture, power/performance, technology, and external partners.
• Influence and improve EDA tools, flows, and PD methodologies using data-driven analysis.
• Communicate project status, risks, and plans clearly to stakeholders and foster collaboration across teams.

Requirements

Key technical and professional requirements. Degrees and fields are summarized separately under Education Requirements.

• Proven hands-on experience in physical design implementation and signoff for SOCs, including synthesis through place-and-route.
• Deep understanding of low-power design techniques and methodology for SOCs; able to perform power analysis and optimization.
• Experience with PPA trade-offs and data-driven optimization approaches.
• Production silicon tape-out experience in advanced foundry process nodes.
• Familiarity with industry-standard power analysis EDA tools (e.g., PrimePower) and physical-design tool flows.
• Strong problem-solving, data analysis, and debugging skills; ability to own technical domain as an individual contributor.
• Effective communicator and collaborator across cross-functional teams; ability to drive results in a matrixed environment.
• Ability to meet Microsoft security screening requirements (Microsoft Cloud Background Check) and comply with export-control documentation and eligibility checks.

Education Requirements

Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field (plus 1+ year technical experience), OR Master’s degree in EE/CE/CS or related (plus 4+ years technical experience), OR Bachelor’s degree in EE/CE/CS or related (plus 5+ years technical experience), OR equivalent practical experience.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.