Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

Owner of end-to-end physical implementation for high-performance interface IPs and subsystems, from RTL through GDS delivery. Work on advanced-node designs and collaborate with front-end, DFT, verification, and foundry teams to achieve signoff-quality results.

Experience Level

Senior — 3+ years of hands-on ASIC physical implementation experience (synthesis, place & route, signoff).

Responsibilities

Deliver physical design on advanced-node interface IPs and subsystems and improve team productivity through automation and methodology improvements.

• Own physical implementation flow: synthesis, floorplanning, placement, CTS, routing, and final GDS delivery.
• Develop timing constraints and drive static timing analysis and closure across corners/modes using PrimeTime.
• Execute power planning and EM/IR analysis with RedHawk; resolve power integrity issues to meet signoff.
• Perform physical verification with IC Validator (ICV); debug and resolve DRC/LVS issues and coordinate with foundry.
• Automate flows and CAD methodology using Tcl, Perl, or Python to reduce manual effort and runtime.
• Collaborate with front-end, DFT, and verification teams to optimize power, performance, and area and ensure clean handoffs.
• Manage hierarchical/subsystem-level integration and ensure top-level signoff across multiple IP blocks.

Requirements

Must-have technical skills and experience for immediate contribution.

• Proven ownership of at least one recent tape-out project carrying physical design responsibilities through GDS delivery.
• Strong working knowledge of PrimeTime (STA), RedHawk (EM/IR), and IC Validator (ICV).
• Experience addressing advanced-node physical design challenges (7nm, 5nm or below) including complex DRC and signoff strategies.
• Proficiency scripting in Tcl, Perl, or Python to build automation and CAD methodology.
• Ability to debug floorplan, congestion, timing, and power issues and communicate tradeoffs to cross-functional teams.
• Nice-to-have: experience with high-performance/high-speed interface IPs (SerDes, DDR, PCIe, or similar).

Education Requirements

B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, or a closely related field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.