Senior Physical Design Engineer
QualcommJob Title
Senior Physical Design Engineer
Role Summary
Own block- and subsystem-level physical implementation on advanced process nodes, delivering timing closure and physical sign-off. Work with front-end, verification, DFT and process teams to resolve design and manufacturing issues and improve implementation flows.
Experience Level
Senior - typically 3–8 years of relevant physical design or backend ASIC experience; candidates with equivalent experience will be considered.
Responsibilities
Primary responsibilities include implementation, analysis, signoff, and automation for high-speed digital blocks and subsystems.
- Lead floorplanning, placement, clock tree synthesis (CTS), routing, and layout optimization for digital blocks and subsystems.
- Drive timing closure: clock skew balancing, OCV handling, multi-corner multi-mode (MCMM) analysis, and ECO implementation.
- Perform signal integrity, power integrity, IR drop, and electromigration analysis using tools such as RedHawk/Voltus.
- Execute full physical signoff flows (DRC, LVS, DFM, EM/IR) and address found issues.
- Develop and maintain backend flows and automation for placement & routing, STA, and physical verification using Python and TCL.
- Optimize power and area with multi-Vt strategies, clock gating, and power-aware synthesis.
- Integrate and evaluate AI-assisted tools for constraint optimization, ECO suggestions, and violation triage.
- Collaborate cross-functionally to resolve design, test, and manufacturing issues.
Requirements
Must-have technical skills and experience. Equivalent practical experience accepted.
- 3–8 years experience in digital physical design / backend methodologies (placement, CTS, PnR, STA).
- Experience with advanced FinFET process nodes (e.g., TSMC N5, N4P, N3 or equivalent).
- Proficiency with EDA signoff and implementation tools: Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk/Voltus.
- Strong scripting skills in Python and TCL for automation and flow development.
- Hands-on flow development: reusable scripts, run environments, and regression frameworks.
- Understanding of IR drop/EM analysis and power optimization techniques.
- Nice-to-have: familiarity with DFT concepts (scan insertion, ATPG, BIST) and exposure to Agentic AI-driven EDA methodologies.
Education Requirements
Bachelor's degree in Science, Engineering, or related field plus 2+ years ASIC experience, OR Master's degree in Science, Engineering, or related field plus 1+ year ASIC experience, OR PhD in Science, Engineering, or related field. Applications with equivalent practical experience will be considered.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
