Senior Physical Design Engineer, Annapurna Labs

Job Title

Senior Physical Design Engineer, Annapurna Labs

Role Summary

Design and optimize physical implementation of custom SoCs used in AWS machine-learning servers (inference and training). Work on RTL-to-GDSII physical implementation, PPA trade-offs, sign-off, and methodology development for cloud-scale accelerators.

Member of the Cloud-Scale Machine Learning Acceleration team; collaborate with RTL, architecture, and verification teams to drive physical design closure and quality at scale.

Experience Level

Senior — experienced engineer expected. See Education Requirements for degree and years-of-experience guidance.

Responsibilities

Deliver physical implementation and drive methodology improvements for custom SoCs.

• Collaborate with RTL and architecture teams to assess architectural feasibility and PPA tradeoffs.
• Drive IO/core/block implementation: synthesis, floor planning, bus/pin planning, place & route.
• Design and analyze power/clock distribution, congestion, timing closure, IR drop, and physical verification to sign-off.
• Perform ECOs and physical sign-off activities; resolve layout-to-tapeout issues.
• Develop and improve physical design methodologies and automation flows.
• Evaluate and integrate 3rd-party IP; specify IP requirements for physical integration.
• Collaborate across teams to prioritize issues and deliver high-quality silicon at scale.

Requirements

Must-have technical skills and experience.

• Extensive ASIC physical design experience (RTL-to-GDSII) on modern process nodes (e.g., 7nm, 14/16nm, 20nm, 28nm).
• Proven experience with industry EDA tools (examples: Cadence, Mentor, Synopsys) across synthesis, P&R, floor planning, and verification flows.
• Expertise in timing closure, congestion analysis, IR drop analysis, power/clock distribution, and physical verification.
• Scripting experience with Python, Perl, Bash, or PowerShell for automation and flow development.
• Experience evaluating and integrating 3rd-party IP and driving physical/IP requirements.
• Strong troubleshooting and QOR analysis skills to identify trends and improve design outcomes.

Nice-to-have:

• Experience mentoring or leading junior engineers.
• Deep knowledge of device physics, custom/semi-custom implementation techniques, and CAD flow development.
• Experience across system technologies (DDR, PCIe, fabrics) and IP integration (4+ years preferred).

Education Requirements

BS in Electrical Engineering or Computer Science plus 8 years of relevant experience, or MS in Electrical Engineering or Computer Science plus 6 years of relevant experience. The posting also specifies 6+ years of ASIC physical design experience (RTL-to-GDSII) as part of the qualifications.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.