Senior Physical Design Engineer, Annapurna Labs

Job Title

Senior Physical Design Engineer, Annapurna Labs

Role Summary

Join the Cloud-Scale Machine Learning Acceleration team to design and optimize physical implementation of custom SoCs used in AWS ML servers (including Inferentia and Trainium systems). The role focuses on RTL-to-GDSII physical implementation, sign-off, methodology development, and integration of IP for large-scale datacenter hardware.

Experience Level

Senior — typically requires substantial hands-on ASIC physical design experience. The posting specifies at least 6+ years of ASIC physical-design experience.

Responsibilities

Key responsibilities focus on driving physical implementation and methodologies for custom SoCs and collaborating with RTL and architecture teams.

• Collaborate with RTL/logic designers to assess architectural feasibility and explore power-performance-area tradeoffs.
• Drive IO/core subsystem and block physical implementation from synthesis through GDSII: floorplanning, bus/pin planning, place & route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, ECO and sign-off.
• Perform timing, IR/EM, and physical verification sign-off activities and resolve closure issues.
• Develop and improve physical-design methodologies and automation flows.
• Evaluate, specify, and integrate 3rd-party IP; define IP requirements for physical implementation.
• Analyze quality-of-results (QoR) metrics, extract design parameters, and track trends to guide optimization.
• Work closely with cross-functional teams and contribute to a collaborative engineering environment.

Requirements

Must-have technical skills and domain experience, plus preferred qualifications that improve fit for the role.

• Must-have: 6+ years of ASIC physical-design experience (RTL-to-GDSII) in advanced technology nodes (examples listed: 7nm, 14/16nm, 20nm, 28nm).
• Must-have: Hands-on experience with EDA tool flows (examples: Cadence, Mentor Graphics, Synopsys) across synthesis, equivalency verification, floor planning, bus/pin planning, place & route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO.
• Must-have: Strong understanding of sign-off activities (timing, IR/EM, physical verification).
• Must-have: Scripting experience with Python, Perl, Bash, or PowerShell.
• Nice-to-have: Experience mentoring, leading, or managing junior engineers.
• Nice-to-have: Experience developing CAD/tool flows and automation for synthesis, floorplanning, P&R, sign-off tasks.
• Nice-to-have: Several years integrating IP and driving physical-domain IP requirements; knowledge of device physics and custom/semi-custom implementation techniques.
• Nice-to-have: Experience addressing physical-design challenges for interfaces such as DDR, PCIe, and fabrics, and experience extracting/using QoR metrics.

Education Requirements

BS + 8 years, or MS + 6 years in Electrical Engineering or Computer Science (EE/CS) as specified in the posting.

Other

Amazon is an equal opportunity employer.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.