Senior Physical Design Engineer

Job Title

Senior Physical Design Engineer

Role Summary

The Senior Physical Design Engineer will lead RTL-to-GDS physical implementation for custom IP and SoC designs, creating manufacturing-ready design databases. This role works within Intel Central Engineering Group on advanced products and custom ASIC customer designs.

The position covers full physical design flow ownership, signoff verification, and methodology/automation improvements; it is eligible for Intel's hybrid work model.

Experience Level

Senior — typically 8–10+ years of hands-on physical design experience (role description specifies Bachelor's +10 years or Master's +8 years).

Responsibilities

Accountable for end-to-end physical design implementation and signoff; expected to drive technical decisions and flow improvements.

• Lead physical implementation from RTL to GDS: synthesis, floorplanning, place & route, clock tree synthesis, and final GDS generation.
• Perform static timing analysis, timing closure, power and noise analysis, and reliability verification for signoff.
• Run verification and signoff flows: formal equivalence, LVS/DRC/layout checks, electrical rule checking, and power integrity analysis.
• Analyze results, identify root causes of violations, and propose fixes that scale across product architectures.
• Optimize designs for power, performance, and area (PPA) and manage multi-power-domain implementations.
• Contribute to development and automation of physical design methodologies and EDA tool flows.

Requirements

Must-have technical skills and practical experience for success in this role.

• Deep knowledge of RTL-to-GDS workflows and physical implementation flows.
• Expertise in PPA optimization techniques and practical trade-offs for power, frequency, and area.
• Hands-on experience with industry-standard EDA tools for physical design, verification, and signoff.
• Strong skills in clock tree design, timing closure, static timing analysis, and floorplanning methodologies.
• Experience with multi-power-domain analysis, low-power design techniques, and DFT integration.
• Experience performing power integrity and noise analysis (static and dynamic).
• Ability to improve and automate design flows and to analyze and remediate complex design issues.
• Nice-to-have: demonstrated cross-functional collaboration, strong problem-solving and communication skills.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (posted with a 10+ years experience expectation). Alternatively, a Master’s degree in a related field is listed with an 8+ years experience expectation. No specific certifications were mandated in the posting.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.