Senior Physical Design AI/ML Engineer (Logic Pathfinding Lab)

Job Title

Senior Physical Design AI/ML Engineer (Logic Pathfinding Lab)

Role Summary

Full-time technical role in the Logic Pathfinding Lab at Samsung Semiconductor in San Jose. The team researches and evaluates advanced device architectures, integration schemes, and exploratory PDKs to support sub-2nm logic node pathfinding and technology transfer to Samsung Logic TD.

The engineer will apply machine learning and generative models to physical-design problems (PPA optimization) and automate flow components to improve design throughput and accuracy.

Experience Level

Senior. The job title indicates senior-level responsibilities; no explicit years-of-experience requirement was listed.

Responsibilities

Key responsibilities include research, model development, and automation across design and verification flows.

• Design, build, and implement ML and generative models to optimize chip layouts for performance, power, and area (PPA) while respecting hardware design rules and constraints.
• Automate and accelerate design implementation steps such as floor-planning, placement & routing, and clock tree synthesis using exploratory PDKs.
• Automate verification steps including Design Rule Checks (DRC) and Layout versus Schematic (LVS) using exploratory PDKs.
• Collaborate to automate exploratory PDK generation and develop automated QA/validation systems.
• Apply ML techniques to correlate data across domains (device, RO benchmark circuits, larger blocks, operating conditions) for predictive modeling and surrogate models.
• Develop internal benchmarking and assessment capabilities based on available data and multi-source modeling.
• Perform other assigned technical tasks that support pathfinding and technology evaluation.

Requirements

Must-have technical skills and behaviors are listed first; preferred skills follow.

• Must-have: RTL synthesis, place-and-route, and timing-analysis experience.
• Must-have: Understanding of clocking schemes and power delivery network design.
• Must-have: Hands-on experience with machine learning or deep learning applied to scientific or engineering problems (e.g., regression, surrogate modeling, inverse design, graph neural networks).
• Must-have: Strong programming skills in Python and/or C++; experience with ML frameworks such as PyTorch or TensorFlow.
• Must-have: Experience using Bayesian optimization and/or active learning for design-space exploration.
• Must-have: Familiarity with agentic AI frameworks named in the posting (examples: LangGraph, CrewAI, ADK).
• Behavioral: Collaborative, inclusive, adaptive, curious, and comfortable working with cross-functional and global teams.
• Nice-to-have: Proficiency with EDA tools for synthesis and layout.
• Nice-to-have: Experience applying generative AI to chip design and optimization.
• Nice-to-have: Familiarity with state-of-the-art AI workload compute and memory requirements and experience optimizing local/private compute clusters for large models.

Education Requirements

PhD preferred; industry experience preferred. The posting does not specify other degree levels or fields of study, nor explicit 'equivalent experience' language.

About the Company

Company: Samsung Semiconductor

Headquarters: San Diego, California, United States

Samsung Semiconductor is a global leader in semiconductor technology, providing innovative solutions for diverse applications including smartphones, electric vehicles, and data centers. As part of Samsung's Advanced Institute of Technology, the company focuses on cutting-edge research in areas such as CPU microarchitecture, AI, and HPC, fostering a diverse and inclusive work environment for its employees to thrive and innovate.