Senior PDK Physical Verification Engineer

Job Title

Senior PDK Physical Verification Engineer

Role Summary

Lead development and deployment of density-fill methodologies and Process Design Kit (PDK) solutions for advanced semiconductor nodes. Work at the intersection of process technology, physical verification, and design automation to improve manufacturability and design productivity.

Experience Level

Senior-level. Typical industry experience expectation is 6+ years; see Education Requirements for degree-to-experience equivalents.

Responsibilities

Primary technical and collaboration duties:

• Design, implement, validate, and deploy density fill solutions within PDKs for advanced nodes.
• Develop algorithmic and methodology solutions using physical verification platforms (Calibre, Synopsys ICV, Cadence Pegasus).
• Collaborate with process integration, design-rule owners, product engineers, and customers to define requirements and deliver solutions.
• Automate workflows to improve efficiency, scalability, and cross-environment deployment.
• Create validation frameworks, test suites, and qualification methodologies for tool and rule deck releases.
• Advance physical verification methodologies to address scaling and manufacturability challenges.
• Partner with external EDA vendors to influence and deploy tool capabilities and methodologies.
• Produce technical documentation, training materials, and best practices for adoption across design teams.
• Serve as a technical expert and contribute to strategic design-enablement initiatives.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 4+ years hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus) including methodology development, rule deck debugging, validation, or production deployment.
• 3+ years developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, PVL, or Tcl-based environments.
• Experience with semiconductor process technology, device physics, design rules, and manufacturability requirements.
• Proven ability to develop algorithmic solutions for physical design and manufacturing challenges at advanced nodes.
• Familiarity with Unix/Linux engineering environments and scripting for automation.
• Strong technical communication, debugging, and analytical skills.

Nice-to-have:

• Direct experience developing, deploying, or supporting density fill methodologies for advanced technologies (notably 16nm and below).
• Experience with physical verification flows including DRC, density analysis, and process-aware design enablement.
• Familiarity with custom layout environments (Cadence Virtuoso, Synopsys Custom Designer).
• Experience leading technical initiatives or working with foundries, IDMs, OSATs, or EDA vendors on PDKs or DFM solutions.

Education Requirements

Bachelor's in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 6+ years of relevant experience; OR Master's with 5+ years; OR PhD with 2+ years. Requirements may be met through a combination of industry experience, internships, coursework, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.