Senior or Principal DSP/FPGA Engineer

Job Title

Senior or Principal DSP/FPGA Engineer

Role Summary

The Senior or Principal DSP/FPGA Engineer will design, implement, and verify high-speed FPGA and signal-processing solutions for tactical wireless communications systems. This role works across algorithm development, hardware implementation, and lab verification within a fast-paced startup environment.

Experience Level

Senior-level. Typical guidance: 5+ years of high-speed FPGA design experience.

Responsibilities

Accountable for end-to-end FPGA/DSP development and verification for communications products; collaborate with systems and test engineers to deliver production-capable designs.

• Architect, implement, and optimize high-speed FPGA designs for signal processing applications.
• Develop and validate DSP algorithms; perform MATLAB-based modeling and simulation.
• Perform hardware bring-up, verification, and debugging in the electronics/RF lab using scopes, spectrum analyzers, and vector signal analyzers.
• Translate algorithms into fixed-point implementations and analyze computational complexity and resource usage.
• Integrate FPGA designs with RF/wireless subsystems and tactical waveforms.
• Document designs, test procedures, and verification results; support product maturation and handoff.
• Take ownership of tasks and operate independently in a small-team startup environment.

Requirements

Key qualifications and compliance requirements. Items marked as "nice-to-have" are preferred but not mandatory.

• Must-have: 5+ years of high-speed FPGA design and implementation experience.
• Must-have: Experience with RF/wireless communications; tactical waveform experience strongly preferred.
• Must-have: Hands-on electronics lab experience and ability to use RF test equipment (oscilloscope, spectrum analyzer, vector signal analyzer).
• Must-have: Eligible as a US Person and able to obtain and maintain a Secret-level clearance (post-hire); must pass a Commercial Background Investigation (CBI).
• Nice-to-have: Strong DSP fundamentals (time/frequency analysis, digital filtering/resampling, fixed-point processing) and algorithm development experience.
• Nice-to-have: Proven MATLAB modeling and simulation skills for signal-processing algorithms.
• Willingness to travel approximately 5–10%.

Education Requirements

MS or PhD preferred. Bachelor’s degree considered when paired with at least 5 years of FPGA design experience; equivalent practical experience acceptable per employer discretion.

Additional Information

Location: Tampa Bay area (Palm Harbor, FL) with hybrid and remote arrangements possible. Employment status: full-time with benefits.

Employer: Pareto Frontier, LLC - a startup focused on tactical wireless communications and defense/aerospace solutions.

About the Company

Company: Pareto Frontier

Headquarters: Palm Harbor, FL, USA

Startup technology solutions firm developing advanced capabilities for tactical wireless communications and other defense & aerospace applications. Works on FPGA/DSP-centric systems and provides engineering R&D services.