Senior Mixed-Signal Physical Design Engineer
QualcommJob Title
Senior Mixed-Signal Physical Design Engineer
Role Summary
Join Qualcomm's Mixed-Signal IP Physical Design team in Cork to lead and execute analog/mixed-signal physical design for next-generation SerDes, Sensors and DDR IP in advanced process nodes (3nm and below). The role combines hands-on implementation, timing/power closure, physical verification and automation, and requires collaboration with global teams.
Experience Level
Senior level. The posting indicates a typical range of 3–7 years in physical design; Qualcomm will consider equivalent experience and candidates with advanced degrees and less experience (see Education Requirements).
Responsibilities
Key responsibilities include leading and delivering mixed-signal physical design projects and collaborating across global sites.
- Lead and perform placement, clock tree synthesis (CTS), routing and static timing analysis (STA) for mixed-signal IP in advanced nodes.
- Drive timing closure, timing signoff methodologies and OCV/AOCV flows.
- Design and analyze power distribution networks; evaluate power/performance/area trade-offs and IR drop mitigation.
- Implement low-power techniques and clocking structures (clock mesh, multi-source CTS).
- Perform or supervise physical verification (DRC/LVS) and other layout checks.
- Develop automation and debugging scripts/tools to improve physical design flows.
- Coordinate and lead cross-site engineering efforts to deliver projects to closure.
Requirements
Essential technical skills and experience required for the role.
- Proven experience in physical design implementation for advanced technologies (placement, CTS, STA) on complex PHYs and subsystems.
- Experience with custom physical design: pre-placement and pre-routing techniques.
- Strong understanding of STA tools, timing closure methodologies and timing implications in mixed-signal designs.
- Power grid analysis experience and familiarity with IR drop and power reduction methods.
- Practical knowledge of clock tree structures and their implications on timing and power.
- Experience with physical verification flows (DRC/LVS) and signoff checks.
- Programming/scripting skills (Tcl, Perl and/or C) and experience delivering automation in physical design.
- Strong verbal and written communication skills and a proven record of delivering physical design projects.
- Ability to lead projects and collaborate with diverse global teams.
- Nice-to-have: EDA tool experience and prior leadership of multi-site physical design projects.
Education Requirements
Bachelor's degree in Science, Engineering or a related field is listed as a baseline. Alternatives noted: Master's degree or PhD in Science/Engineering or related field may be acceptable with fewer years of experience. The posting also states that equivalent practical experience will be considered in lieu of formal degrees.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
