Senior Methodologist for AIML Enhanced Design/Verification

Job Title

Senior Methodologist for AIML Enhanced Design/Verification

Role Summary

Senior engineer responsible for architecting, building, and maintaining AIML-enhanced solutions for digital design and verification flows. Work with design, system, and verification teams to improve verification closure from RTL through tapeout.

Experience Level

Senior. Role expects multi-year experience: typically 5–7 years in RTL design/verification infrastructure plus 3–5 years applying AIML methods to design or verification problems.

Responsibilities

The role focuses on integrating AIML into verification and design processes and delivering measurable improvements in verification productivity and silicon quality.

• Architect, develop, and maintain AIML/agentic solutions, skills, and APIs for design and verification infrastructure.
• Create or enhance UVM-based testbenches and verification plans with clear coverage goals and closure criteria.
• Perform root-cause analysis for failures and collaborate with design teams to drive fixes to closure.
• Automate generation of RTL from specifications and build AIML-assisted flows to accelerate implementation/verification tasks.
• Evaluate and recommend industry tools and platforms for simulation, emulation, formal, and AIML integration.
• Maintain and scale verification infrastructure across projects; promote reusable methodology and best practices.

Requirements

Core technical and experience requirements.

Must-have:

• 3–5 years of hands-on experience applying AIML methods, including creating agents, skills, models, and APIs for design/verification use cases.
• 5–7 years of production experience developing RTL design and verification infrastructure.
• Strong SystemVerilog skills for design or verification.
• Solid understanding of digital design fundamentals: RTL, timing, and synthesis constraints.
• Experience with industry simulators (examples: Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Effective written and verbal communication; experience collaborating in cross-functional teams.

Nice-to-have:

• Experience with formal verification tools and techniques.
• Experience with emulation and FPGA prototyping platforms (Palladium, Protium, Veloce).
• Publications or conference presentations in design/verification methodology or AIML applications.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent practical experience). Preferred: Master's or Ph.D. in Electrical Engineering or Computer Science. Equivalent hands-on experience is explicitly accepted.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.