Senior Memory Post Silicon Qualification Engineer

Job Title

Senior Memory Post Silicon Qualification Engineer

Role Summary

Owner for high-speed memory bring-up, characterization, and qualification for GPU, CPU, and SoC programs inside the Silicon Co-Design Group. The role focuses on root-causing ambiguous memory marginality across DRAM, controller, PHY, package, board, firmware, and workloads, and on building repeatable, AI-enabled qualification workflows and playbooks.

Experience Level

Senior. Requires 10+ years in the semiconductor industry with at least 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon.

Responsibilities

Primary responsibilities include hands-on bring-up, qualification, cross-team debugging, and automation of analysis workflows.

• Bring up GDDR, LPDDR, and HBM interfaces from first power-on through full PVT characterization and productization on complex GPU, CPU, and SoC silicon.
• Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across memory controller, PHY, and DRAM devices for all supported capacities, speeds, and configurations.
• Lead root-cause closure for complex multi-domain memory failures and produce reusable workarounds and productized fixes.
• Design and deploy AI-enabled workflows for margin data analysis, shmoo bucketing, failure signature detection, and workload-vs-margin correlation with guardrails for decision-ready outputs.
• Partner with pre-Si architecture, design, and DV teams to translate features into targeted post-Si validation plans and feed learnings back into pre-Si methodology.
• Collaborate with globally distributed teams, DRAM vendors, and manufacturing partners across Taiwan and other hubs.

Requirements

Must-have technical experience and demonstrated track record.

• 10+ years in the semiconductor industry and a minimum of 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon.
• Deep protocol and physical-layer expertise with GDDR, LPDDR, or HBM, including training, calibration, IO tuning, timing margin analysis, and vendor-to-vendor behavior; demonstrated example of taking an ambiguous memory failure to root cause and delivering a productized fix.
• Strong hands-on lab skills: oscilloscopes, DMMs, thermal chambers, protocol analyzers; practical knowledge of PCB stack-up, board layout, power planes, and SI/PI as they affect memory behavior.
• Proven experience building AI-driven workflows or tools for memory characterization, margin analysis, or failure triage with measurable adoption beyond the individual contributor.

Nice-to-have:

• History of building reusable qualification methodology, debug playbooks, or margin-analysis frameworks adopted by other programs.
• AI work beyond individual assistance (agentic workflows, RAG-grounded debug assistants, automated shmoo analysis, ML-driven margin prediction) deployed at team scale with adoption metrics.

Education Requirements

B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.