Senior Memory Design Engineer

Job Title

Senior Memory Design Engineer

Role Summary

Senior engineer responsible for leading design and delivery of high-speed memory blocks and compiler components (SRAM, register files) for advanced process nodes. Works with circuit, timing, and layout teams to meet performance, yield, and sign-off targets.

Experience Level

Senior-level. Typical guidance from the posting: 4+ years with a Master’s degree or 5+ years with a Bachelor’s degree.

Responsibilities

Primary responsibilities include design, verification, characterization, and production readiness of memory compilers and key memory circuits.

• Lead design and development of single-/multiport SRAM and register-file compilers for 28nm, 16FF, 7FF, and 5FF process nodes.
• Circuit design and transistor-level simulation of bitcell, word-line decoder, sense amplifier (SAMP), column decoder, and control logic.
• Develop critical-path and characterization flows for margin and performance simulations.
• Perform statistical analysis of bit-cell and sense amplifier behavior to support compiler yield sign-off.
• Tune designs, perform margin analysis, and drive compiler-level sign-off for yield and performance targets.
• Perform logic simulations and detailed timing analysis of high-speed memory paths.
• Perform signal-integrity (EM) and power-integrity (IR drop) analysis and mitigation.
• Debug silicon failures, analyze root causes, and implement fixes; collaborate on silicon bring-up and validation.
• Coordinate with layout teams to address sub-nanometer layout-related issues affecting memory designs.

Requirements

Must-have technical skills and tools for the role; nice-to-have items listed separately.

• Must-have: Expertise in high-speed, low-power CMOS circuit design, clocking schemes, and static/dynamic logic.
• Must-have: Experience designing and driving memory compiler specifications through to release.
• Must-have: Hands-on experience with Cadence or Mentor schematic/layout editor tools and circuit simulation flows (HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewers, or equivalent).
• Must-have: Hands-on silicon debug and failure analysis experience.
• Must-have: Understanding of layout challenges at advanced nodes and how they impact circuit behavior.
• Must-have: Knowledge of split-rail and power-gating architectures and their circuit implementations.
• Nice-to-have: Skill with scripting (Skill, Perl, Python) to automate flows and analyses.
• Nice-to-have: Familiarity with Memory DFT techniques.

Education Requirements

Master's degree with 4+ years of relevant experience, or Bachelor's degree with 5+ years of relevant experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.