Senior Mask Layout Design Engineer
Design and implement mask-level physical layouts for high-speed mixed-signal circuits (PLLs, SerDes, high-speed memory I/O, general I/Os, ESD) in advanced sub-micron CMOS FinFET processes. The role partners with ASIC and mixed-signal teams to integrate custom blocks into VLSI products and ensure rule and schematic compliance.
Position is part of a layout engineering group focused on production-quality mixed-signal IP for NVIDIA ASICs.
Senior β typically requires a minimum of 5 years of relevant mask design/layout experience.
Primary responsibilities include:
Must-have skills and experience:
Nice-to-have:
Bachelor of Science in Electrical Engineering (BSEE) is specified; minimum 5 years of relevant mask design/layout experience or equivalent practical experience is acceptable.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
