Senior Manager, Silicon Speed Productization - Silicon Co-Design Group
NVIDIAJob Title
Senior Manager, Silicon Speed Productization - Silicon Co-Design Group
Role Summary
Lead a globally distributed team that owns simulation-to-silicon speed correlation and productization across GPU, CPU, and SoC programs. The team identifies mismatches between predicted and measured silicon performance, drives root-cause closure, and defines product limits, guardbands, binning, and production sign-off.
This is a hands-on technical management role: you will both set technical direction and remove the toughest speed risks to ensure programs meet frequency, voltage, temperature, workload, and lifetime targets.
Experience Level
Senior - requires extensive experience. The role expects significant domain expertise and proven people leadership.
Responsibilities
Own end-to-end speed characterization, correlation, and productization; deliver decision-ready analysis and build scalable workflows.
- Lead simulation-to-silicon speed correlation from pre-silicon planning and first power-on through production sign-off.
- Drive root-cause analysis and closure for frequency misses, timing escapes, voltage-margin issues, and workload-model divergence.
- Define and validate product limits: margining, PVT characterization, guardbands, aging, and binning strategies.
- Embed measured-silicon feedback into timing models, test content, and design practices to improve future correlation.
- Present characterization data, model deltas, yield trends, and risks as concise options for leadership decisions.
- Scale coverage and cycle time via automation, data pipelines, and AI-assisted workflows for test orchestration and anomaly detection.
- Recruit, develop, and retain a high-performing team; mentor senior engineers and first-line managers.
Requirements
Core technical, analytical, and leadership capabilities required to lead silicon speed productization.
Must-have:
- 12+ years in silicon characterization, post-silicon validation, timing or performance analysis, with substantial hands-on technical scope.
- 5+ years leading technical teams; proven experience developing senior engineers and first-line managers.
- Deep knowledge of digital design, computer architecture, static timing analysis, critical-path behavior, and clocking.
- Expertise in simulation-to-silicon correlation, voltage-frequency margining, guardbanding, and PVT/binning dependencies.
- Demonstrated ability to drive ambiguous, system-level problems to root-cause closure across multiple organizations.
- Proficiency with data-analysis and automation tools such as Python, SQL, JMP, or equivalents; ability to interpret large silicon datasets and distinguish correlation from causation.
- Strong written and verbal communication; able to translate technical issues into decision-ready options for leadership.
Nice-to-have:
- Experience applying AI to characterization or debug workflows.
- History of building reusable correlation or margining methodologies adopted across programs or process nodes.
- Evidence of tracing frequency misses to specific critical paths, microarchitectural interactions, or process corners and delivering productized fixes.
Education Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Systems Engineering, or equivalent practical experience.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
