Senior Manager, Embedded Memory

Job Title

Senior Manager, Embedded Memory

Role Summary

Lead the architecture, circuit design, and delivery of Silvaco's embedded memory compiler portfolio (SRAM, ROM, 1PRF/2PRF, DPRAM). Manage a team of memory designers, own the technical roadmap, and act as the senior technical interface to customers from presales through silicon qualification.

This is a hands-on technical leadership role combining memory design, PPA optimization, customer engagement, and team management to ensure production-ready memory compilers across process nodes.

Experience Level

Senior — typically 10+ years of embedded memory design and production tapeout experience.

Responsibilities

Accountabilities span technical design leadership, team management, customer engagements, and PPA benchmarking.

• Lead architecture, circuit design, and physical implementation for SRAM, ROM, single- and dual-port register files, and dual-port RAM compilers.
• Define bitcell selection, peripheral architecture, redundancy/repair, and assist circuits to meet PPA targets across PVT corners.
• Establish and own design, verification, and signoff methodology (SPICE/FastSPICE, Monte Carlo, BIST, DFT, physical verification).
• Drive Vmin, leakage, area, performance, yield, and reliability optimization and manage silicon validation and testchip efforts.
• Lead, mentor, and allocate work for a cross-functional team of memory designers, layout engineers, and characterization engineers.
• Act as senior technical lead in presales: translate SoC requirements into compiler specs, support RFQs, and lead technical workshops with customers.
• Own PPA analysis and competitive benchmarking; produce datasheets, application notes, and white papers from analysis results.
• Serve as primary technical contact for customers through integration, tapeout, and silicon correlation; coordinate root-cause analysis across teams.

Requirements

Must-have technical skills, tools experience, leadership and customer-facing capabilities. Preferred items are noted separately.

• Must-have: 10+ years of embedded memory design with demonstrated production tapeouts of SRAM and at least two among ROM, 1PRF, 2PRF, DPRAM.
• Deep expertise in bitcell circuit design, sense amplifiers, decoders, write drivers, self-timing, and assist techniques.
• Experience across multiple process nodes, including FinFET and advanced sub-7nm technologies.
• Strong SPICE/FastSPICE simulation skills; statistical/Monte Carlo analysis; Vmin, yield, and reliability (BTI/HCI/EM) modeling.
• Working knowledge of memory compiler architecture and automation, including generated views (.lib, LEF, GDS, Verilog, CDL) and scaling across configurations.
• Hands-on experience with DFT/scan tools, power signoff tools, layout verification flows (DRC/LVS/PEX), and RTL/Verilog memory modelling.
• Proven team leadership managing or technically leading teams of ~6+ memory designers and strong customer-facing experience (presales, PPA negotiation, integration support).
• Proficiency with scripting (Python, TCL, Perl) and Linux-based design environments; familiarity with AI assistance tools.
• Experience interfacing with foundry partners on PDK, bitcell qualification, and reference flow alignment; prior industry presentations/publication experience.
• Nice-to-have: experience with multi-port (>2) memories, specialty memories (TCAM, multi-bank arrays), and low-power memory design for mobile/IoT/automotive/AI workloads.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field (required in the posting). The listing specifies degrees in EE/CE or related technical disciplines.

About the Company

Company: Silvaco

Headquarters: Santa Clara, California, United States

Provider of TCAD and EDA software and services for semiconductor device/process simulation, device characterization, and design enablement, supporting manufacturing, R&D, and IC design workflows.