Senior Manager, Design Verification Engineering

Job Title

Senior Manager, Design Verification Engineering

Role Summary

Lead Design Verification efforts for digital IP and subsystems within the Digital Systems IP team (Engineering Enablement). Responsible for DV strategy, verification execution, cross-functional collaboration, and delivering validated IP across the product lifecycle.

Experience Level

Senior — requires extensive leadership and technical experience. The posting specifies at least 15 years of ASIC design verification experience.

Responsibilities

Accountable for verification strategy, team leadership, and delivery of IP verification for SoC use cases.

• Define verification strategy, test plans, and methodologies for IP and chip-level verification.
• Verify complex digital designs and subsystems using constrained-random, coverage-driven, assertion-based, and formal techniques.
• Manage, mentor, and grow a high-performing DV engineering team; plan resources and track execution.
• Collaborate with design, architecture, firmware, and product teams to develop test plans and close functional/code coverage.
• Support processor-based verification and gate-level simulation flows for SoC verification.
• Work with business units that use IP to understand SoC use cases and adapt DV accordingly.
• Drive continuous improvement of verification tools, flows, and processes.

Requirements

Key technical and managerial requirements. "Nice-to-have" items are noted.

• Minimum ~15 years of ASIC design verification experience.
• Proven experience managing teams of ~20+ engineers.
• Deep expertise in constrained-random verification, functional/code coverage, assertion-based methods, and formal verification.
• Experience with mixed-signal simulators (e.g., Cadence Xcelium) and analog behavioral modeling.
• Experience applying AI tools to verification workflows.
• Proficiency in Verilog, SystemVerilog, C/C++, SystemC, Java, TCL, Perl, Python, and shell scripting.
• Strong communication and leadership skills; ability to define and execute verification strategies across teams.
• Required travel: approximately 10%.
• Nice-to-have: Property Specification Language (PSL), MATLAB (co-simulation/HDL generation), DSP experience, low-power methodologies such as CPF and UPF.

Education Requirements

Bachelor's or Master's degree in Electronic Engineering or a related field. The posting specifies this academic requirement in combination with the experience requirement noted above.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.