Senior Manager, Analog Layout Design

Job Title

Senior Manager, Analog Layout Design

Role Summary

Lead a small analog layout team within Central Engineering to deliver physical layout solutions for high-speed, mixed-signal, and advanced-technology integrated circuits. The role combines technical leadership, people management, project execution, and methodology development to support multiple product generations and process nodes.

Experience Level

Senior — the posting specifies 10+ years of analog layout design experience and 3+ years in a leadership role.

Responsibilities

Accountable for team leadership, project delivery, technical correctness, and continuous improvement of layout practices.

• Lead, mentor, and develop a team of analog layout engineers; manage performance, hiring, onboarding, and succession planning.
• Plan layout execution, allocate resources, manage schedules, and ensure timely completion of layout milestones.
• Provide technical guidance for analog and mixed-signal layout in advanced technologies (FinFET, CMOS, BiCMOS).
• Oversee layout reviews to ensure compliance with design requirements, foundry rules, reliability, and manufacturability.
• Drive implementation of matching, shielding, isolation, noise mitigation, electromigration/EMIR, ESD protection, and other physical constraints.
• Collaborate with circuit design, physical design, CAD, verification, reliability, and program management teams throughout development and silicon bring-up.
• Lead methodology, automation, reusable IP strategies, verification flows, and adoption of new EDA tools and workflows.

Requirements

Key qualifications and skills required for successful performance in this role.

• Must have: 10+ years of analog layout design experience and 3+ years managing teams, projects, or technical execution.
• Must have: Hands-on expertise with analog/high-speed/mixed-signal layout (examples: SerDes, PLLs, ADCs/DACs, TIAs, drivers, clocking, power management).
• Must have: Proven track record of multiple successful tapeouts on advanced FinFET process nodes.
• Must have: Proficiency with industry EDA tools such as Cadence Virtuoso, Calibre, PVS, StarRC, or equivalents.
• Must have: Deep understanding of device physics, parasitics, matching, shielding, isolation, reliability, EM/IR, ESD, and manufacturability best practices.
• Must have: Strong project management, prioritization, problem-solving, communication, and cross-functional collaboration skills.
• Nice to have: Experience developing layout methodology, automation, reusable IP, and evaluation/deployment of new EDA technologies.
• Nice to have: Experience with BiCMOS processes, yield improvement initiatives, and post-tapeout debug and root-cause analysis.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related technical field (BS/MS) as stated in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.