Senior Logic/DSP Design Engineer – Mixed Signal

Job Title

Senior Logic/DSP Design Engineer – Mixed Signal

Role Summary

Design and implement digital logic and DSP algorithms for mixed-signal IP blocks (high-speed SerDes, ADC/DAC digital, calibration engines, control logic). Collaborate with analog/mixed-signal architects to integrate digital and analog subsystems and support silicon bring-up and verification.

Team: Analog Mixed Signal Serdes (AMS).

Experience Level

Senior — typically requires 7+ years of relevant experience in digital logic design with mixed-signal or DSP exposure.

Responsibilities

Primary responsibilities include translating system/DSP algorithms into synthesizable RTL and ensuring the digital portion meets timing, power, and verification targets within a mixed-signal flow.

• Micro-architect and implement RTL for mixed-signal subsystems (calibration state machines, digital filters, adaptive equalizers, CDR loops, etc.).
• Define digital-analog interfaces, calibration flows, and control logic in collaboration with analog teams.
• Perform RTL-to-gate synthesis, timing closure, and apply low-power techniques for mixed-signal blocks.
• Develop and maintain block-level verification environments for mixed-signal verification and AMS co-simulation.
• Support silicon bring-up and debug; correlate digital behavior with analog lab measurements.
• Document architecture and design decisions; participate in design and code reviews.
• Mentor junior engineers on digital design practices in a mixed-signal context.

Requirements

Must-have technical skills and experience.

• 7+ years of experience in digital logic design with exposure to mixed-signal or DSP projects.
• Strong RTL design skills in Verilog and practical synthesis flow experience.
• Solid understanding of DSP fundamentals: filtering, sampling, quantization, timing recovery.
• Familiarity with mixed-signal verification methodologies (AMS simulation, Verilog-AMS, real number modeling).
• Experience with RTL-to-gate flow, timing closure and low-power design techniques.
• Ability to support silicon bring-up and collaborate with lab teams for debugging.

Nice-to-have:

• Experience with high-speed SerDes, PCIe, DisplayPort, Ethernet or similar protocols.
• Exposure to calibration/adaptation algorithms for ADCs, DACs, or equalizers.
• Familiarity with static timing analysis (STA) and low-power methodologies.
• Prior experience working directly with analog designers on digital-analog co-design.

Education Requirements

BSc or MSc in Electrical Engineering is specified.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.