Senior Logic Design Engineer

Job Title

Senior Logic Design Engineer

Role Summary

Experienced RTL designer responsible for defining micro-architecture and delivering production-quality RTL for complex digital blocks in memory and high-performance digital IP. Individual contributor working with architecture, verification, physical design, applications, and customer-facing engineering teams.

Role supports next-generation memory subsystems and high-performance interfaces for data center, HPC, and AI applications. Hybrid position based in San Jose, CA or Hillsboro, OR with roughly three onsite days per week.

Experience Level

Senior-level — typically 8+ years of ASIC/FPGA logic design experience; individual contributor with significant technical ownership.

Responsibilities

Primary duties include architecture, RTL implementation, and cross-discipline integration.

• Define micro-architecture and implement production-quality SystemVerilog/Verilog RTL for complex digital blocks.
• Design scheduling logic, command/transaction pipelines, ordering/coherency mechanisms, control logic, and high-performance system interfaces.
• Evaluate performance, power, and area (PPA) trade-offs and use quantitative analysis to guide decisions.
• Partner with verification to develop strategies, identify corner cases, and improve coverage.
• Collaborate with physical design to address timing closure, power, utilization, and routing/congestion.
• Investigate regressions, perform root-cause analysis, and implement RTL fixes.
• Participate in design reviews and cross-functional architecture discussions.
• Support customer-facing engineering during technical evaluations and assist applications/product teams with integration and post-delivery issues.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Strong expertise in SystemVerilog and Verilog RTL design.
• Extensive experience developing complex ASIC and/or FPGA logic (design and implementation).
• Familiarity with industry-standard simulators such as Questa, Xcelium/Incisive, or VCS.
• Proficiency with scripting languages (Python, Perl, and/or Tcl) for design/automation tasks.
• Deep understanding of digital design principles, micro-architecture, timing, and hardware implementation.
• Ability to analyze complex technical problems independently and drive them to resolution.
• Strong written and verbal communication skills and ability to collaborate across engineering teams.
• Track record of managing technical priorities and delivering designs on schedule.
• Nice-to-have: experience with memory controllers, high-performance interconnects, cache/coherency architectures, or data-center silicon.

Education Requirements

BSEE with 10+ years of relevant ASIC/FPGA logic design experience, or MSEE with 8+ years of relevant ASIC/FPGA logic design experience.

About the Company

Company: KPG99

Technical staffing and recruiting firm that places contract engineering talent, including ASIC/SoC verification and other hardware and firmware roles.