Senior/Lead STA Engineer

Job Title

Senior/Lead STA Engineer

Role Summary

The Senior/Lead Static Timing Analysis (STA) Engineer drives timing analysis and closure for high-performance SoC designs across block, cluster, and full‑chip hierarchies. This role collaborates with RTL, physical design (PD), DFT and CAD teams to meet aggressive frequency and power targets and leads an STA team for assigned projects.

Experience Level

Senior-level. Preferred experience 5–9 years in STA and timing closure; minimum qualification options: Bachelor's +3 years, Master’s +2 years, or PhD +1 year of relevant hardware engineering experience.

Responsibilities

Key responsibilities include detailed timing analysis, driving fixes, and coordinating across design teams.

• Perform STA at block, cluster, and SoC/top-level hierarchies across modes, corners, and scenarios.
• Analyze frequency‑critical paths and recommend logic or micro‑architectural fixes with RTL and DFT teams.
• Define, implement, and validate timing constraints in collaboration with RTL designers (DDR, PCIe, UCIe, etc.).
• Provide actionable timing feedback to block and top‑level physical design engineers.
• Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross‑talk violations.
• Lead and mentor an STA team for assigned project delivery and signoff.

Requirements

Must-have technical skills and attributes; listed succinctly.

• Proven hands‑on STA experience and timing closure for high‑performance SoCs, including signoff‑quality closure on large CPU/SoC designs.
• Expertise in multi‑clock, multi‑domain designs and identifying frequency‑critical paths.
• Familiarity with timing effects: noise, cross‑talk, OCV/variation, and corner selection for signoff.
• Experience with STA tools such as Tempus and PrimeTime.
• Scripting proficiency (Perl, Tcl, Awk or similar) for automation and analysis.
• Knowledge of standard cell libraries, synthesis, tape‑out flows, and interaction with PD/CAD flows.
• Strong communication skills to coordinate with RTL, PD, CAD, and DFT teams and to drive ECOs.
• Leadership ability to lead an STA team and deliver project milestones.

Education Requirements

Degree required: Bachelor's, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, or related engineering field. Minimum experience varies by degree: Bachelor's +3 years, Master’s +2 years, PhD +1 year. Preferred candidates often have 5–9 years of STA/timing closure experience. Equivalent practical experience may be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.