Senior Lead Engineer - SoC Design Verification

Job Title

Senior Lead Engineer - SoC Design Verification

Role Summary

Hands-on design verification lead responsible for SoC and IP verification for microcontroller-class SoCs. Owns verification suites, drives DV closure, debugs RTL/netlist simulations and mentors junior engineers.

Works with architects and design teams to implement verification plans, run regressions across RTL, power-aware RTL, gate-level and emulation platforms, and improve flows for reuse and efficiency.

Experience Level

Senior — typically 5–12 years of SoC/IP verification experience (the posting references 6+ years). Experience with successful SoC tape-outs is expected.

Responsibilities

Primary responsibilities include delivering SoC/IP verification and ensuring quality and coverage to sign-off standards.

• Develop and own SoC-level and IP-level verification suites and meet coverage goals.
• Execute verification plans derived from product specifications and architect requirements.
• Develop, debug and run UVM-based verification environments for RTL and netlist simulation.
• Define and implement test cases, create stimulus and assertions, run regressions, and analyze functional/code coverage.
• Perform verification across models: RTL, power-aware RTL, gate-level, FPGA, and emulation platforms.
• Drive DV closure for diverse IPs and subsystems; coordinate with design teams for issue resolution and sign-off.
• Improve verification flows for reuse and efficiency; promote best practices.
• Mentor and train junior verification engineers.

Requirements

Must-have technical capabilities and relevant experience. Education details are listed below under Education Requirements.

• 5–12 years of SoC/IP verification experience with participation in successful SoC tape-outs.
• Proficiency in Verilog, SystemVerilog and UVM; experience with constrained-random verification.
• Experience with C-based DV at the SoC level.
• Familiarity with EDA simulators such as Synopsys VCS and Cadence Xcelium.
• Strong knowledge of assertions (SVA) and functional coverage methodologies.
• Experience debugging simulations and running regressions across RTL/netlist/gate-level/emulation platforms.
• Good communication skills and ability to work in fast-paced, collaborative teams; mentoring experience preferred.
• Nice-to-have: low-power verification (UPF), gate-level and power-aware simulation experience, verification of interfaces (SPI, I2C, UART, USB, PCIe, Ethernet, CAN, eSPI), Flash/security IP knowledge, and common analog IPs (ADC, DAC, PLLs).

Education Requirements

Bachelor's or Master's degree in Microelectronics, Electronics, or Electrical Engineering.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.