Senior Lead, DFT and Test Engineer

Job Title

Senior Lead, DFT and Test Engineer

Role Summary

Lead DFx Center of Excellence activities to ensure board-level testability and maximum test coverage are designed into hardware prior to layout freeze. The role performs pre-freeze audits, coverage modeling against the Manufacturing Test Requirements Specification (MTRS), and works with design and software teams to disposition issues and close DFT findings.

Located in Richardson, TX; this position focuses on testability as a design attribute (not test development or fixture design).

Experience Level

Senior-level. Typical experience: 4–8 years in Design for Testability (DFT) or Test Engineering in complex electronics environments.

Responsibilities

Primary responsibilities include pre-layout testability reviews, coverage analysis, and driving closure of DFT issues to achieve high first-pass coverage.

• Perform pre-freeze audits of schematics and PCB layouts against the core DFT rule set and document technical findings.
• Model structural and functional test coverage versus the MTRS and quantify coverage gaps.
• Work with hardware and software teams to disposition findings: add test points, correct boundary-scan chains, or agree design alternatives.
• Verify achieved coverage on the first physical fixture and document discrepancies against pre-layout claims.
• Support site-level functional test definition and early build debug with Technical Region Leads and local SMEs.
• Propose targeted updates to the DFT rule set based on test escapes and post-build rework.
• Produce formal testability review reports, coverage models mapped to the MTRS, and empirical evidence packages for first-fixture coverage.

Requirements

Must-have technical skills and experience required to perform the role.

• Proven background in Design for Testability (DFT) with board-level schematic and high-density PCB layout review experience.
• Experience evaluating and troubleshooting boundary-scan chains, debug/provisioning access, and test-point accessibility.
• Practical knowledge of MTRS-based coverage modeling, functional test strategy, and hardware bring-up processes.
• Ability to document technical findings with supporting evidence and to collaborate directly with cross-functional hardware and software teams.
• Strong problem-solving skills and experience closing DFT findings prior to layout freeze.
• Occasional travel as required; primarily office-based work in a standard office environment.
• Nice-to-have: hands-on exposure to first-fixture validation and empirical coverage verification.

Education Requirements

Bachelor's degree in Electrical Engineering, Electronic Engineering, or a related technical discipline.

About the Company

Company: Celestica

Headquarters: Toronto, Ontario, Canada

Global design, engineering, and manufacturing services company providing hardware, supply chain and platform solutions for data center, aerospace, defense, healthtech and advanced electronics customers. Offers engineering-led services across design, manufacturing, and lifecycle support with a global network.