Senior Lead Design Engineer - RTL Design

Job Title

Senior Lead Design Engineer - RTL Design

Role Summary

Principal individual-contributor role providing hands-on technical leadership for RTL architecture, design, integration, and delivery of next-generation FPGA and programmable SoC solutions. The role drives RTL microarchitecture, implementation strategies, and execution across complex subsystems and global engineering teams.

Focus areas include high-throughput datapaths, memory and interconnect subsystems, packet/data processing, and programmable acceleration with emphasis on performance, power, timing, and product readiness.

Experience Level

Senior / Principal-level individual contributor. Posting specifies 15+ years of relevant FPGA, ASIC, SoC, or semiconductor product development experience.

Responsibilities

Deliver and lead RTL design and integration across complex programmable-device subsystems; set technical direction and ensure quality from concept through silicon delivery.

• Lead RTL architecture, microarchitecture, and implementation for high-performance datapaths, memory access, interconnect, and acceleration subsystems.
• Own RTL design for critical blocks and subsystem integrations; ensure code is reusable, synthesizable, scalable, and testable.
• Define design specs, interface contracts, clocking/reset strategies, performance targets, and implementation plans that align cross-functional teams.
• Drive tradeoffs across throughput, latency, buffering, power, area, timing, reliability, and schedule; identify and mitigate risks early.
• Establish and advance RTL methodologies: coding standards, lint, CDC/RDC, synthesis flows, formal/equivalence checks, and automation.
• Partner with verification, physical design, DFT, CAD, firmware, and system validation to preserve design intent through timing closure and silicon bring-up.
• Lead root-cause analysis and debug of complex integration and performance issues, using data-driven decisions.
• Provide technical mentorship, conduct architecture and RTL/code reviews, and raise engineering quality across teams.

Requirements

Must-have technical skills and experience required to perform the role; preferred skills listed separately.

• Deep hands-on RTL expertise in Verilog and/or SystemVerilog, including synthesis-aware coding and implementation-aware design practices.
• Experience with synthesis flows, lint, CDC/RDC analysis, and formal or equivalence checking.
• Proven track record designing high-performance digital subsystems (network/data pipelines, memory controllers/subsystems, on-chip interconnect, traffic management).
• Experience with interfaces and protocols such as PCIe/CXL, Ethernet, and other high-speed connectivity.
• Strong systems judgment on tradeoffs involving bandwidth, latency, congestion, buffering, throughput, power, area, timing, and reliability.
• Experience leading multi-block design execution, technical planning, risk management, schedule alignment, and prioritization across teams.
• Demonstrated cross-functional collaboration and influence with verification, physical design, DFT, CAD, firmware/software, and product teams; strong written and verbal communication skills.
• Nice-to-have: experience with FPGA architecture RTL, reusable IP across products, high-bandwidth memory, FPGA prototyping/emulation/silicon bring-up, scripting for automation (Python, Tcl, Perl, shell), and a record of patents/publications or standards contributions.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline. Advanced degree (MS/PhD) preferred. The posting specifies 15+ years of relevant industry experience but does not state an explicit "equivalent experience" substitution for the degree requirement.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.