Senior Lead Design Engineer

Job Title

Senior Lead Design Engineer

Role Summary

Senior individual-contributor and technical leader responsible for architecture, design, and delivery of high-performance FPGA and programmable SoC subsystems. The role drives architecture and RTL implementation decisions across product generations and cross-functional global teams.

Experience Level

Senior - typically 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development.

Responsibilities

Key responsibilities include technical leadership from architecture through product readiness:

• Lead architecture, microarchitecture, and RTL development for complex datapaths, interconnect, memory access, and acceleration subsystems.
• Define technical requirements, interfaces, and architectural specifications that align hardware, firmware, software, validation, and product objectives.
• Drive tradeoffs across performance, power, area, latency, bandwidth, reliability, and schedule using data-driven analysis.
• Own critical blocks through RTL implementation, synthesis, integration, verification support, timing closure, bring-up, and performance characterization.
• Establish reusable IP, coding standards, automation, and quality methodologies to improve engineering velocity and first-pass success.
• Partner with verification, physical design, DFT, CAD, firmware/software, emulation, prototyping, board, and post-silicon teams to maintain architectural intent.
• Lead resolution of complex cross-functional issues, perform root-cause analysis, and make technical decisions to mitigate risk.
• Provide technical mentorship, conduct architecture and code reviews, and influence engineering roadmaps and external IP/tool choices.

Requirements

Must-have skills and experience:

• Proven technical leadership delivering complex digital subsystems from architecture through RTL, verification, integration, and hardware validation.
• Deep hands-on expertise in Verilog and/or SystemVerilog RTL design, synthesis, lint, CDC/RDC, formal or equivalence checking, and timing-constraint-aware design.
• Experience with high-performance digital architectures such as networking/datapaths, offload engines, PCIe/CXL, Ethernet, DDR/HBM, high-speed interfaces, or on-chip interconnects.
• Strong understanding of performance, power, area, timing, bandwidth, latency, congestion, and reliability tradeoffs in advanced digital systems.
• Experience planning and executing design across multiple functional blocks or chip-level integration, including risk management and schedule alignment.
• Ability to collaborate and influence across architecture, RTL, verification, physical design, CAD, firmware/software, system validation, and product teams; strong written and verbal communication skills.
• Must be eligible for any required U.S. export authorizations.

Preferred (nice-to-have):

• Experience in FPGA architecture, programmable-logic devices, SmartNICs, IPUs, or data-center acceleration platforms.
• Track record building reusable design IP and experience with FPGA prototyping, emulation, silicon bring-up, or post-silicon debug.
• Proficiency with scripting and automation (Python, Tcl, Perl, shell) and experience mentoring teams in a matrixed environment.
• Record of innovation (patents, publications, standards contributions) is a plus.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline is required. An advanced degree is preferred. The role expects approximately 15+ years of relevant FPGA/ASIC/SoC or semiconductor product development experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.