Senior Layout Engineer - DPG LPDDR

Job Title

Senior Layout Engineer - DPG LPDDR

Role Summary

Responsible for custom analog and mixed-signal physical layout for LPDDR PHY blocks to achieve robust silicon performance across PVT and high-volume manufacturability.

Work within a cross-functional SoC/PHY team to deliver first-silicon success for LPDDR products, focusing on signal integrity, matching, power distribution, and layout-aware co-design.

Experience Level

Senior-level. The posting expects 6+ years of relevant hands-on experience in analog/mixed-signal layout and high-speed interfaces.

Responsibilities

Main responsibilities include:

• Own custom analog and mixed-signal layout of LPDDR PHY blocks: datapath, bias networks, IO analog front-ends, and reference circuits.
• Execute high-speed LPDDR interface layout addressing skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
• Design array-based layouts for DQ/DQS byte lanes, CA lanes, and replica paths with strict symmetry and pitch matching for multi-byte/channel scaling.
• Implement custom digital block layouts within the PHY (training logic, calibration engines, test/debug circuits) while managing clocking and congestion near analog regions.
• Drive layout-aware co-design with circuit designers to meet timing, noise, IR, and EM constraints; incorporate parasitic-awareness early.
• Perform DRC/LVS closure, parasitic extraction reviews, and correlate layout results with simulation for silicon-accurate performance.
• Support post-layout optimization and ECOs to address margin, yield, and manufacturability issues while maintaining JEDEC compliance.
• Contribute to PPA optimization with emphasis on low power, area efficiency, and reliability for LPDDR applications.
• Share knowledge and improve layout flows, best practices, and review processes to enable first-silicon success.

Requirements

Must-have technical skills and experience:

• 6+ years of hands-on analog/mixed-signal layout experience, including high-speed serial interfaces.
• Proven experience with LPDDR PHY layout, high-speed IO layout techniques, and multi-byte PHY scalability.
• Strong skills in skew control, impedance matching, shielding, crosstalk mitigation, and jitter-aware layout.
• Experience with power distribution, grounding, isolation techniques (guard rings, deep-N-well), and decoupling strategies.
• DRC/LVS closure, parasitic extraction, and correlation with circuit/signal integrity simulation tools.
• Experience performing post-layout ECOs, yield-driven fixes, and ensuring manufacturability under JEDEC constraints.
• Ability to collaborate with architecture, circuit, verification, and silicon debug teams; strong communication skills.

Nice-to-have:

• Experience with layout automation, data-driven optimization, or AI/ML-assisted layout flows.
• Prior work on LPDDR family products at advanced process nodes and familiarity with VXL-compatible flows or similar production flows.

Education Requirements

B.Tech / B.E. in Electronics, Electronics & Communications, or VLSI Engineering; M.Tech in Electronics Engineering, Microelectronics, or VLSI Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.