Senior Layout Engineer - DPG LPDDR

Job Title

Senior Layout Engineer - DPG LPDDR

Role Summary

Design and own custom analog and mixed-signal layout for LPDDR PHY blocks (datapath, IO analog frontends, bias and reference circuits) with emphasis on robustness across PVT, low-noise coupling and high matching accuracy. Work cross-functionally with architecture, circuit, verification and silicon debug teams to achieve first-silicon success and high-volume manufacturability.

Experience Level

Senior — typically 6+ years of hands-on analog/mixed-signal and high-speed layout experience (LPDDR or similar interfaces).

Responsibilities

Key responsibilities:

• Own custom analog and mixed-signal layout of critical LPDDR PHY blocks, ensuring robustness across PVT, low noise coupling, and matching accuracy.
• Execute high-speed LPDDR interface layout addressing skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
• Design and optimize array-based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths with strict symmetry, pitch matching, repeatability and scalability.
• Implement custom digital block layouts within the LPDDR PHY (training logic, calibration engines, test/debug circuitry) while managing clocking, congestion and interaction with sensitive analog regions.
• Drive layout-aware co-design with circuit designers to meet timing, noise, IR and EM requirements, incorporating parasitic awareness early in the design cycle.
• Apply best practices for power distribution, grounding and isolation (guard rings, deep-N-well, decoupling strategies, domain separation) to protect analog and high-speed signals.
• Perform DRC/LVS closure, parasitic extraction reviews and correlate post-layout results with simulations; support post-layout ECOs to resolve margin, yield and manufacturability issues.
• Contribute to PPA optimization with focus on low-power operation, area efficiency and reliability for LPDDR applications.
• Promote knowledge sharing, contribute to layout flows and automation efforts, and leverage AI/ML as a value-add for layout automation and data-driven optimization.

Requirements

Must-have technical skills and experience:

• Proven hands-on analog and mixed-signal layout experience for high-speed serial interfaces; LPDDR PHY experience preferred.
• Strong signal-integrity-aware layout techniques: skew control, impedance matching, shielding, crosstalk mitigation and jitter sensitivity handling.
• Experience designing pitch-matched, symmetric array layouts for byte lanes and multi-channel configurations.
• Experienced with power distribution, grounding, isolation techniques and decoupling strategies for sensitive analog/high-speed regions.
• Practical experience with DRC/LVS closure, parasitic extraction, post-layout correlation and ECO implementation.
• Familiarity with JEDEC compliance and manufacturability considerations for memory interfaces.

Nice-to-have:

• Experience applying AI/ML to layout automation, optimization or debug workflows.
• Experience with layout-aware parasitic-aware co-design and PPA tradeoffs in advanced process nodes.
• Experience with VXL-compatible flows or similar layout automation frameworks.

Education Requirements

B.Tech / B.E in Electronics, Electronics & Communications, or VLSI Engineering; M.Tech in Electronics, Microelectronics or VLSI Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.