Senior Layout Engineer – DPG Layout

Job Title

Senior Layout Engineer – DPG Layout

Role Summary

Design and implement block-level analog, mixed-signal, and custom-digital layouts for advanced CMOS processes, owning quality and delivery for assigned blocks. Work within a layout team that supports full-chip integration, verification closure, and collaboration with Design, Verification, and CAD groups.

Micron is an equal-opportunity employer; reasonable accommodation requests are handled separately.

Experience Level

Senior-level. The posting requests 3+ years of experience in analog/custom layout design; role expects demonstrated ownership of block-level layout and verification.

Responsibilities

Primary technical responsibilities and team interactions:

• Execute block-level layout for analog, mixed-signal, and custom-digital blocks, delivering manufacturable designs that meet design intent.
• Perform layout verification tasks (DRC, LVS, antenna checks) and lead closure for assigned blocks.
• Apply layout techniques for matching, symmetry, electromigration, latch-up prevention, IR-drop, coupling, crosstalk, and parasitics to meet performance and yield targets.
• Use semicustom tools to support ECOs, alignment, and integration-level updates during block integration.
• Develop or apply AI-assisted methods and prompt-based tools to generate/refine SKILL/Python/TCL scripts and automate repetitive layout and verification work to improve consistency and throughput.
• Communicate layout status, risks, and integration issues to design, verification, CAD, and senior engineers.
• Review and mentor less-experienced layout engineers, sharing techniques and guidance on producing robust layouts.

Requirements

Core technical qualifications and desirable experience.

Must-have:

• 3+ years of hands-on analog/custom layout experience in advanced CMOS processes.
• Proven experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.
• Experience laying out critical analog and mixed-signal blocks (examples include PLLs, ADCs, DACs, LDOs, bandgaps, references, charge pumps, temperature sensors).
• Solid understanding of analog layout fundamentals: matching/symmetry, electromigration, latch-up, IR-drop, coupling, crosstalk, and parasitic effects.
• Ability to translate design constraints into manufacturable layouts and assess layout impact on speed, capacitance, power, and area.
• Practical experience developing or applying AI-driven automation and AI-assisted methodologies to improve layout efficiency and quality.
• Strong problem-solving skills for physical layout verification and debug.

Nice-to-have:

• Exposure to memory layout environments such as DRAM, SRAM, CAM, or OTP.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.