Senior Layout Engineer — DPG Layout

Job Title

Senior Layout Engineer — DPG Layout

Role Summary

Implement and deliver block-level physical layouts for analog, mixed-signal, and custom digital blocks and support full-chip integration in advanced CMOS processes. Work within a layout team and coordinate with Design, Verification, and CAD to meet quality and schedule targets.

Experience Level

Senior role. Requires at least 3+ years of hands-on experience in analog/custom layout design in advanced CMOS processes.

Responsibilities

Execute and verify block-level layouts and support integration tasks. Key responsibilities include:

• Implement physical layouts for analog, mixed-signal and custom digital blocks with attention to design intent, manufacturability, and quality.
• Own layout execution for assigned blocks, meeting turnaround and quality expectations.
• Perform layout verification: DRC, LVS, antenna checks, and yield/quality checks; debug verification issues.
• Use prompt-based AI tools to generate or refine SKILL/Python/TCL scripts and automate repetitive layout and verification tasks.
• Support semicustom tools and ECO processes to accelerate integration and alignment tasks between custom and digital domains.
• Collaborate with design, verification, CAD, and senior layout engineers to communicate status and risks.
• Review sub-block layouts from less-experienced engineers and share techniques to improve team capability.

Requirements

Must-have technical skills and experience; listed "nice-to-have" items are indicated.

• Must-have: 3+ years of analog/custom layout design experience in advanced CMOS processes.
• Must-have: Hands-on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.
• Must-have: Experience laying out critical analog/mixed-signal blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, and charge pumps.
• Must-have: Strong understanding of analog layout fundamentals: matching and symmetry, electromigration, latch-up, IR-drop, coupling, crosstalk, and parasitic effects.
• Must-have: Ability to interpret design constraints and translate them into robust, manufacturable layouts with attention to speed, capacitance, power, and area trade-offs.
• Must-have: Practical experience applying or developing AI-driven automation and AI-assisted methodologies to improve layout efficiency and consistency.
• Must-have: Strong problem-solving skills for physical layout verification and debug.
• Nice-to-have: Exposure to memory layout environments (DRAM, SRAM, CAM, OTP).

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.