Senior Layout Engineer - DPG Layout

Job Title

Senior Layout Engineer - DPG Layout

Role Summary

Design and execute block-level physical layouts for analog, mixed-signal, and custom digital blocks and support full-chip integration. Work within a layout team to deliver manufacturable, high-quality layouts and collaborate with design, verification, and CAD engineers.

Experience Level

Senior level; the posting requests ~3+ years of experience in analog/custom layout design in advanced CMOS process.

Responsibilities

Deliver block-level layouts, verification, and integration support with emphasis on quality, turnaround, and manufacturability.

• Implement physical layouts for analog, mixed-signal, and custom digital blocks and support their full-chip integration.
• Own block-level layout execution, meeting design intent, schedules, and quality targets.
• Perform layout verification activities including DRC, LVS, antenna checks, and yield/quality assessments.
• Use prompt-based AI tools to generate or refine SKILL/Python/TCL scripts and automate repetitive layout and verification tasks.
• Support semicustom integration and ECO flow to accelerate alignment and integration-level updates.
• Collaborate with design, verification, CAD, and senior layout engineers to communicate status and risks.
• Review and mentor junior engineers on sub-block layout techniques and best practices.

Requirements

Key technical skills and experience required or strongly preferred.

• Minimum ~3 years practical experience in analog/custom layout design in advanced CMOS processes.
• Hands-on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS; responsible for verification and closure for assigned blocks.
• Experience laying out critical analog/mixed-signal blocks such as PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps, temperature sensors.
• Solid understanding of layout fundamentals: matching/symmetry, electromigration, latch-up, IR-drop, coupling, crosstalk, and parasitics and their impact on performance.
• Ability to translate design constraints into robust, manufacturable layouts considering speed, capacitance, power, and area trade-offs.
• Hands-on experience developing or applying AI-driven automation and AI-assisted methodologies for layout and verification tasks.
• Familiarity with semicustom tools and flows to support ECOs and integration-level updates is desirable.
• Strong problem-solving skills for physical layout verification and debug; ability to communicate technical issues clearly.

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.