Senior Layout Engineer - DPG Layout

Job Title

Senior Layout Engineer - DPG Layout

Role Summary

Execute block-level physical layout for analog, mixed-signal and custom digital blocks and support full-chip integration. Own layout quality, schedule and verification closure while collaborating with design, verification and CAD teams.

Experience Level

Senior. The posting specifies at least 3+ years of analog/custom layout experience in advanced CMOS processes.

Responsibilities

Primary responsibilities include block implementation, verification, automation and mentoring.

• Perform block-level layout for analog, mixed-signal and custom digital circuits and deliver manufacturable layouts on schedule.
• Execute layout verification tasks (DRC, LVS, antenna checks) and lead verification closure for assigned blocks.
• Apply layout techniques addressing matching, symmetry, electromigration, latch-up, IR drop, coupling and parasitic effects.
• Use and develop automation (SKILL/Python/TCL) and prompt-based AI tools to reduce repetitive tasks and improve consistency.
• Support semicustom integration and ECO acceleration for custom/digital interfaces at integration level.
• Collaborate with Design, Verification and CAD; communicate status and risks; assist in reviewing and mentoring less-experienced engineers.

Requirements

Must-have technical skills and experience, followed by desirable skills.

• Must-have: Hands-on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS and ownership of verification/closure for assigned blocks.
• Must-have: Experience laying out critical analog/mixed-signal blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators and charge pumps.
• Must-have: Solid understanding of analog layout fundamentals and the impact of layout on speed, capacitance, power and area; strong physical layout verification and debug skills.
• Must-have: Ability to interpret design constraints and produce robust, manufacturable layouts.
• Must-have: Experience applying AI-driven automation or AI-assisted methodologies to physical layout tasks.
• Nice-to-have: Exposure to memory layout environments (DRAM, SRAM, CAM, OTP) and experience with semicustom tools to accelerate ECOs and integration updates.

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.