Senior Layout Engineer

Job Title

Senior Layout Engineer

Role Summary

Responsible for physical implementation, layout development, and verification of high-performance RF and mixed-signal integrated circuits. Work with RFIC designers, process and product engineers to translate schematics into manufacturable silicon meeting performance, reliability, area, and yield targets.

Role includes EM modelling, physical verification, methodology development, and cross-functional support from concept through tapeout. Travel up to 10% and daytime shift.

Experience Level

Senior-level. Typical experience: 3–5 years in RFIC, analog, or mixed-signal physical design.

Responsibilities

Primary responsibilities include physical layout, verification, EM support, and methodology development for RFICs.

• Develop and implement physical layouts for RF, analog, mixed-signal, and passive circuit blocks.
• Floorplanning and device placement to optimize RF performance, matching, isolation, and manufacturability.
• Design high-frequency routing: transmission lines, transformers, inductors, baluns, and matching networks.
• Create custom layouts for LNAs, mixers, PAs, VCOs, PLLs, switches, and other RF building blocks.
• Perform physical verification (DRC, LVS, ERC, antenna and density checks) and ensure compliance with foundry/process rules.
• Support post-layout extraction, parasitic analysis, and collaborate with designers to resolve LVS and performance issues.
• Generate and optimize layouts for RF passives and support EM simulation methodologies.
• Develop reusable layout cells, best practices, and layout methodologies; explore AI-assisted layout improvements.
• Participate in design reviews, tapeout readiness assessments, silicon debug, and cross-functional collaboration with CAD, verification, process, and test teams.

Requirements

Must-have technical skills and experience for the role; preferred skills listed separately.

• 3–5 years of hands-on RFIC, analog, or mixed-signal physical/layout design experience.
• Experience with advanced CMOS, SiGe BiCMOS, SOI, or RF CMOS process technologies.
• Strong understanding of RF layout techniques, parasitic effects, and high-frequency electromagnetic behaviour.
• Experience with physical verification flows and foundry rule compliance (DRC, LVS, ERC, antenna, density checks).
• Proficiency with Cadence Virtuoso Layout Suite.

Nice-to-have:

• Experience with Keysight ADS and Cadence EMX.
• Experience designing RF passives from sub-GHz to mmWave and supporting foundry tapeouts.
• Scripting experience (SKILL, Python, Perl, TCL) to automate layout tasks.
• Familiarity with automotive, industrial, consumer, or wireless communication product requirements.

Education Requirements

Bachelor's degree in Electrical Engineering, Electronics Engineering, Physics, or a related field (as stated). No explicit mention of equivalent-experience language or higher-degree requirements.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.