Senior Layout Designer - Pathfinding

Job Title

Senior Layout Designer - Pathfinding

Role Summary

Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor devices from schematics and geometry provided by design engineers. Lead major block developments, verify data integrity, and coordinate with TD, design, verification, and CAD teams across global sites.

Drive layout methodology improvements and automation; work independently and adapt to changing priorities.

Experience Level

Senior-level. Role requires demonstrated leadership on complex layout projects and strong technical problem-solving skills.

Responsibilities

Primary responsibilities include layout delivery, verification, and process improvement across globally distributed teams.

• Develop and prepare multi-dimensional layouts and detailed drawings from schematics and provided geometry.
• Lead planning, scheduling, and delivery of major blocks and product revisions; assign resources and provide direction.
• Improve layout efficiency through automation and new methodologies; develop custom layout, floor‑planning, signal‑planning, and power‑planning strategies.
• Perform physical verification analysis, debug layout issues, and verify data integrity and design rule compliance.
• Organize and prioritize logistics and resources to meet deadlines and resolve issues.
• Collaborate with design, verification, TD, and CAD teams in a globally distributed environment.

Requirements

Must-have technical skills and capabilities; degree and years-of-experience are listed under Education Requirements.

• Deep working knowledge of EDA tools such as Cadence Virtuoso, Synopsys, and Calibre.
• In-depth understanding of design rules and delivering high-quality layouts.
• Strong physical verification analysis and debugging skills; root-cause problem solving.
• Experience developing layout automation and methodologies to improve throughput.
• Skilled in custom layout techniques including floor‑planning, signal‑planning, and power‑planning.
• Ability to communicate and collaborate across global functional teams.

Nice-to-have:

• Project leadership experience focused on quality optimization and die-size reduction.
• IC layout experience with NAND, DRAM, and/or SRAM.
• Programming skills and experience leveraging AI to support layout workflows.

Education Requirements

AS or Bachelors degree in Electronics, Electrical Engineering, or a related field plus 5 years of direct semiconductor layout design experience (minimum qualification from the posting).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.