Senior Layout Design Engineer

Job Title

Senior Layout Design Engineer

Role Summary

Design and own full-custom analog and IO physical layouts for GPIO, specialty IO and general-purpose analog IP. Deliver manufacturable, reliable layouts that meet area, matching, performance and ESD/latchup constraints.

Work with a global IP development team on interface IP (I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG), LVDS and crystal oscillator circuits, and build reusable layout automation and methodologies.

Experience Level

Senior - the posting lists 3–6 years of hands-on analog/mixed-signal layout experience and expects senior-level responsibilities such as mentorship and technical leadership.

Responsibilities

Primary responsibilities include block-level and full-custom layout, verification, automation and cross-site coordination.

• Design and own full-custom analog layouts for GPIO, specialty IO and general-purpose analog IP (I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG).
• Develop LVDS and crystal oscillator layouts with attention to signal integrity, noise coupling and parasitic management.
• Perform layout verification (DRC, LVS) and parasitic extraction analysis; iterate with designers to meet performance targets.
• Build and maintain layout automation and check scripts to improve efficiency and consistency across IP families.
• Provide technical guidance and conduct layout reviews and mentorship for junior engineers.
• Collaborate with global teams to align on design standards, schedules and deliverables for multi-site IP programs.

Requirements

Must-have technical skills and practical experience; nice-to-have items listed below.

• 3–6 years of hands-on analog or mixed-signal custom IC layout experience.
• Strong understanding of CMOS layout fundamentals: device matching, parasitics, electromigration, latchup and ESD protection strategies.
• Proficiency with industry-standard layout and verification tools such as Cadence Virtuoso and Calibre (or equivalents).
• Experience with parasitic extraction tools and the ability to interpret R/C extraction results to meet circuit performance targets.
• Scripting experience for layout automation and design checks (Python, Perl, TCL, SKILL).

Nice-to-have:

• Experience with IO frame design, pad ring assembly and specialty interface IP layout.
• Prior work on high-performance LVDS, crystal oscillators, or other signal-integrity-sensitive circuits.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, VLSI Design, or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.